Component sync_Reset_Altera

Block Diagram of sync_Reset_Altera

Generics

Name	Type	Initial Value	Description
SYNC_DEPTH	T_MISC_SYNC_DEPTH	low	generate SYNC_DEPTH many stages, at least 2

Ports

Name	Direction	Type	Description
Clock	in	std_logic	<Clock> output clock domain
Input	in	std_logic	@async: reset input
Output	out	std_logic	@Clock: reset output

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