Entity sync_Bits

Block Diagram of sync_Bits

This module synchronizes multiple flag bits into clock-domain Clock. The clock-domain boundary crossing is done by two synchronizer D-FFs. All bits are independent from each other. If a known vendor like Altera or Xilinx are recognized, a vendor specific implementation is chosen.

Attention

Use this synchronizer only for long time stable signals (flags).

Constraints:

General:

Please add constraints for meta stability to all '_meta' signals and timing ignore constraints to all '_async' signals.

Xilinx:

In case of a Xilinx device, this module will instantiate the optimized module PoC.xil.sync.Bits. Please attend to the notes of sync_Bits.vhdl.

Altera sdc file:

TODO

SeeAlso: PoC.misc.sync.Reset

For a special 2 D-FF synchronizer for reset-signals.

PoC.misc.sync.Pulse

For a special 1+2 D-FF synchronizer for pulse-signals.

PoC.misc.sync.Strobe

For a synchronizer for strobe-signals.

PoC.misc.sync.Vector

For a multiple bits capable synchronizer.

Generics

Name	Type	Default	Description
BITS	positive	1	number of bit to be synchronized
INIT	std_logic_vector	x"00000000"	initialization bits
SYNC_DEPTH	T_MISC_SYNC_DEPTH	low	generate SYNC_DEPTH many stages, at least 2

Ports

Name	Type	Direction	Description
Clock	std_logic	in	<Clock> output clock domain
Input	std_logic_vector	in	@async: input bits
Output	std_logic_vector	out	@Clock: output bits

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