Component uart_bclk

Block Diagram of uart_bclk

Bit Clock Generator: 8 Ticks per Bit

Generics

Name	Type	Initial Value	Description
CLK_FREQ	positive
BAUDRATE	positive

Ports

Name	Direction	Type	Description
clk	in	std_logic
rst	in	std_logic
bclk	out	std_logic
bclk_x8	out	std_logic

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