Component uart_fifo

Block Diagram of uart_fifo

Wrappers

UART with FIFOs and optional flow control

Generics

Name	Type	Initial Value	Description
CLOCK_FREQ	FREQ		Communication Parameters
BAUDRATE	BAUD
TX_MIN_DEPTH	positive	16	Buffer Dimensioning
TX_ESTATE_BITS	natural	0
RX_MIN_DEPTH	positive	16
RX_FSTATE_BITS	natural	0
FLOWCONTROL	T_IO_UART_FLOWCONTROL_KIND	UART_FLOWCONTROL_NONE	Flow Control
SWFC_XON_CHAR	std_logic_vector ( 7 downto 0 )	x"11"	^Q
SWFC_XON_TRIGGER	real	0.0625
SWFC_XOFF_CHAR	std_logic_vector ( 7 downto 0 )	x"13"	^S
SWFC_XOFF_TRIGGER	real	0.75

Ports

Name	Direction	Type	Description
Clock	in	std_logic
Reset	in	std_logic
TX_put	in	std_logic	FIFO interface
TX_Data	in	std_logic_vector
TX_Full	out	std_logic
TX_EmptyState	out	std_logic_vector
RX_Valid	out	std_logic
RX_Data	out	std_logic_vector
RX_got	in	std_logic
RX_FullState	out	std_logic_vector
RX_Overflow	out	std_logic
UART_RX	in	std_logic	External Pins
UART_TX	out	std_logic

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