Component uart_rx

Block Diagram of uart_rx

Receiver

Generics

Name	Type	Initial Value	Description
SYNC_DEPTH	natural	2	use zero for already clock-synchronous rx

Ports

Name	Direction	Type	Description
clk	in	std_logic	Global Control
rst	in	std_logic
bclk_x8	in	std_logic	Bit Clock and RX Line bit clock, eight strobes per bit length
rx	in	std_logic
do	out	std_logic_vector	Byte Stream Output
stb	out	std_logic

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