[source]

Component uart_tx

clkstd_logicrststd_logicbclkstd_logicdi[7 downto 0]std_logic_vectorputstd_logictxstd_logicfulstd_logic

Block Diagram of uart_tx

Transmitter

Ports

Name

Direction

Type

Description

clk

in

std_logic

Global Control

rst

in

std_logic

bclk

in

std_logic

Bit Clock and TX Line bit clock, one strobe each bit length

tx

out

std_logic

di

in

std_logic_vector

Byte Stream Input

put

in

std_logic

ful

out

std_logic