Entity uart_bclk

Block Diagram of uart_bclk

old comments:

UART BAUD rate generator bclk_r = bit clock is rising bclk_x8_r = bit clock times 8 is rising

Generics

Name	Type	Default	Description
CLOCK_FREQ	FREQ	100 MHz
BAUDRATE	BAUD	115200 Bd

Ports

Name	Type	Direction	Description
clk	std_logic	in
rst	std_logic	in
bclk	std_logic	out
bclk_x8	std_logic	out

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