[source]

Entity uart_tx

clkstd_logicrststd_logicbclkstd_logicdi[7 downto 0]std_logic_vectorputstd_logictxstd_logicfulstd_logic

Block Diagram of uart_tx

UART Transmitter: 1 Start + 8 Data + 1 Stop

Ports

Name

Type

Direction

Description

clk

std_logic

in

Global Control

rst

std_logic

in

bclk

std_logic

in

Bit Clock and TX Line bit clock, one strobe each bit length

tx

std_logic

out

di

std_logic_vector

in

Byte Stream Input

put

std_logic

in

ful

std_logic

out