Architecture rtl of udp_RX

Types

Name	Description
T_STATE

Processes

process @ ( Out_Ack or In_EOF or In_Data or In_Valid or Is_EOF or Is_SOF or Is_DataFlow or State or )

FSM Transitions for State

#	Current State	Next State	Condition
1	ST_IDLE	ST_RECEIVE_SOURCE_PORT_1	[((Is_SOF = '1') and (Is_EOF = '0'))]
2	ST_IDLE	ST_ERROR	[((Is_SOF = '1') and not (Is_EOF = '0'))]
3	ST_RECEIVE_SOURCE_PORT_1	ST_RECEIVE_DEST_PORT_0	[((In_Valid = '1') and (Is_EOF = '0'))]
4	ST_RECEIVE_SOURCE_PORT_1	ST_ERROR	[((In_Valid = '1') and not (Is_EOF = '0'))]
5	ST_ERROR	ST_IDLE	[EMPTY]
6	ST_RECEIVE_DEST_PORT_0	ST_RECEIVE_DEST_PORT_1	[((In_Valid = '1') and (Is_EOF = '0'))]
7	ST_RECEIVE_DEST_PORT_0	ST_ERROR	[((In_Valid = '1') and not (Is_EOF = '0'))]
8	ST_RECEIVE_DEST_PORT_1	ST_RECEIVE_LENGTH_0	[((In_Valid = '1') and (Is_EOF = '0'))]
9	ST_RECEIVE_DEST_PORT_1	ST_ERROR	[((In_Valid = '1') and not (Is_EOF = '0'))]
10	ST_RECEIVE_LENGTH_0	ST_RECEIVE_LENGTH_1	[((In_Valid = '1') and (Is_EOF = '0'))]
11	ST_RECEIVE_LENGTH_0	ST_ERROR	[((In_Valid = '1') and not (Is_EOF = '0'))]
12	ST_RECEIVE_LENGTH_1	ST_RECEIVE_CHECKSUM_0	[((In_Valid = '1') and (Is_EOF = '0'))]
13	ST_RECEIVE_LENGTH_1	ST_ERROR	[((In_Valid = '1') and not (Is_EOF = '0'))]
14	ST_RECEIVE_CHECKSUM_0	ST_RECEIVE_CHECKSUM_1	[((In_Valid = '1') and (Is_EOF = '0'))]
15	ST_RECEIVE_CHECKSUM_0	ST_ERROR	[((In_Valid = '1') and not (Is_EOF = '0'))]
16	ST_RECEIVE_CHECKSUM_1	ST_RECEIVE_DATA_1	[((In_Valid = '1') and (Is_EOF = '0'))]
17	ST_RECEIVE_CHECKSUM_1	ST_ERROR	[((In_Valid = '1') and not (Is_EOF = '0'))]
18	ST_RECEIVE_DATA_1	ST_RECEIVE_DATA_N	[((Is_DataFlow = '1') and (Is_EOF = '0'))]
19	ST_RECEIVE_DATA_1	ST_IDLE	[((Is_DataFlow = '1') and not (Is_EOF = '0'))]
20	ST_RECEIVE_DATA_N	ST_IDLE	[(Is_EOF = '1')]
21	ST_DISCARD_FRAME	ST_ERROR	[(Is_EOF = '1')]

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