[source]

Entity xil_ICAP

ICAP_WIDTHDEVICE_IDSIM_CFG_FILE_NAMEclkstd_logicdisablestd_logicrd_wrstd_logicdata_in[31 downto 0]std_logic_vectorbusystd_logicdata_outstd_logic_vector[31 downto 0]

Block Diagram of xil_ICAP

This module wraps Xilinx "Internal Configuration Access Port" (ICAP) primitives in a generic module. |br| Supported devices are:

  • Spartan-6

  • Virtex-4, Virtex-5, Virtex-6

  • Series-7 (Artix-7, Kintex-7, Virtex-7, Zynq-7000)

Generics

Name

Type

Default

Description
ICAP_WIDTH

string

"X32"

Specifies the input and output data width to be used
DEVICE_ID

bit_vector

X"1234567"

Spartan 6: fixed to 16 bit Virtex 4: X8 or X32 Rest: X8, X16, X32 pre-programmed Device ID value for simulation
SIM_CFG_FILE_NAME

string

"NONE"

supported by Spartan 6, Virtex 6 and above Raw Bitstream (RBT) file to be parsed by the simulation model
Ports

Name

Type

Direction

Description
clk

std_logic

in

up to 100 MHz (Virtex-6 and above, Virtex-5??)
disable

std_logic

in

low active enable -> high active disable
rd_wr

std_logic

in

0 - write, 1 - read
busy

std_logic

out

on Series-7 devices always '0'
data_in

std_logic_vector

in

on Spartan-6 only 15 downto 0
data_out

std_logic_vector

out

on Spartan-6 only 15 downto 0