Entity xil_Reconfigurator

Block Diagram of xil_Reconfigurator

Many complex primitives in a Xilinx device offer a Dynamic Reconfiguration Port (DRP) to reconfigure a primitive at runtime without reconfiguring the whole FPGA.

This module is a DRP master that can be pre-configured at compile time with different configuration sets. The configuration sets are mapped into a ROM. The user can select a stored configuration with ConfigSelect. Sending a strobe to Reconfig will start the reconfiguration process. The operation completes with another strobe on ReconfigDone.

Generics

Name	Type	Default	Description
DEBUG	boolean	FALSE
CLOCK_FREQ	FREQ	100 MHz
CONFIG_ROM	T_XIL_DRP_CONFIG_ROM	(0 downto 0 => C_XIL_DRP_CONFIG_SET_EMPTY)

Ports

Name	Type	Direction	Description
Clock	std_logic	in
Reset	std_logic	in
Reconfig	std_logic	in
ReconfigDone	std_logic	out
ConfigSelect	std_logic_vector	in
DRP_en	std_logic	out
DRP_Address	T_XIL_DRP_ADDRESS	out
DRP_we	std_logic	out
DRP_DataIn	T_XIL_DRP_DATA	in
DRP_DataOut	T_XIL_DRP_DATA	out
DRP_Ack	std_logic	in

• Architecture rtl of xil_Reconfigurator
  • Processes

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