Architecture rtl of xil_Reconfigurator

Types

Name	Description
T_STATE

Processes

process @ ( DRP_Ack or ROM_LastConfigWord or Reconfig or State or )

FSM Transitions for State

#	Current State	Next State	Condition
1	ST_IDLE	ST_READ_BEGIN	[(Reconfig = '1')]
2	ST_READ_BEGIN	ST_READ_WAIT	[EMPTY]
3	ST_READ_WAIT	ST_WRITE_BEGIN	[(DRP_Ack = '1')]
4	ST_WRITE_BEGIN	ST_WRITE_WAIT	[EMPTY]
5	ST_WRITE_WAIT	ST_DONE	[((DRP_Ack = '1') and (ROM_LastConfigWord = '1'))]
6	ST_WRITE_WAIT	ST_READ_BEGIN	[((DRP_Ack = '1') and not (ROM_LastConfigWord = '1'))]
7	ST_DONE	ST_IDLE	[EMPTY]

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