FPGA Support

Intel(Altera) Quartus

Use the New DVT Project Wizard (menu File > New > DVT Project`) to create a DVT project in the same location as an existing Quartus project. All source files and settings defined in the Quartus project configuration files will be automatically recognized.

If you want to create a DVT project in a different location from your Quartus project location you must tune the .dvt/default.build file:

+dvt_init_auto
# Note that the compilation root must be specified after the +dvt_init_auto directive
+dvt_compilation_root+/quartus/project/location

Note

Quartus projects are automatically recognized by the DVT build auto-configuration engine. For more details, see Auto-config. When the auto-configuration algorithm detects a Quartus project layout, it scans the existing Quartus project configuration files and automatically generates an equivalent DVT build configuration file (for example default.build.auto.1).

If there is no Quartus project layout, this functionality can be triggered using the +dvt_autoconfig_force_quartus directive. It allows the auto-configuration algorithm to scan *.qip files specified in default.build using +dvt_autoconfig_quartus_qip+<qip_file_path> directive (see example below):

+dvt_init_auto
+dvt_autoconfig_force_quartus
+dvt_autoconfig_quartus_qip+file1.qip
+dvt_autoconfig_quartus_qip+file2.qip
+dvt_autoconfig_quartus_qip+file3.qip

Note

The New DVT Project Wizard automatically adds both Verilog and VHDL natures. You can manually adjust this setting.

Intel(Altera) Quartus Auto-config Specific Directives

Directive	Description
+dvt_autoconfig_quartus_project_revision+<revision_name>	Use <revision_name>.
+dvt_autoconfig_quartus_script_location+<script_file_path>	For debugging purposes. Use <script_file_path> to analyze Quartus project configuration files.
`+dvt_autoconfig_disable_quartus`	Ignore Quartus project configuration files and fallback to default auto-config.
`+dvt_autoconfig_quartus_qip+<qip_file_path>`	Analyze the specified Quartus project configuration file in addition to any automatically detected ones. May be specified multiple times.
`+dvt_autoconfig_force_quartus`	Force quartus auto-config using the *.qip files specified within the +dvt_init_auto section.
`+dvt_autoconfig_quartus_qip_search_path+<qip_dir_path>`	Specify root paths in which a deep search will be performed for .qip files corresponding to .ip files referenced in Quartus project configuration. Use +dvt_autoconfig_quartus_qip_search_path_add to specify additional directories to be scanned.Use +dvt_autoconfig_quartus_qip_search_path_clear to clear the list of scan roots.
`+dvt_quartus_debug`	Print debug information to the build console during Quartus auto-config.

Intel(Altera) Quartus Libraries Compilation

In order to compile Intel(Altera) Quartus libraries:

specify the required libraries using the +dvt_init_altera directive
specify the Quartus installation path, unless $QUARTUS_ROOTDIR system variable is set

For example:

+dvt_init_altera+ALTERA+ALTERA_MF
+dvt_setenv+QUARTUS_ROOTDIR=/apps/altera/13.0sp1/quartus

The available VHDL libraries are ALTERA_MF, ALTERA, ALTERA_LNSIM, LPM, MAX, MAXII, MAXV, STRATIX, STRATIXII, STRATIXIIGX, HARDCOPYII, HARDCOPYIII, HARDCOPYIV, CYCLONE, CYCLONEII, CYCLONEIII, CYCLONEIIILS, SGATE, STRATIXGX, ALTGXB, STRATIXGX_GXB, STRATIXIIGX_HSSI, ARRIAGX_HSSI, ARRIAII, ARRIAII_HSSI, ARRIAII_PCIE_HIP, ARRIAIIGZ, ARRIAIIGZ_HSSI, ARRIAIIGZ_PCIE_HIP, ARRIAGX, STRATIXIII, STRATIXIV, STRATIXIV_HSSI, STRATIXIV_PCIE_HIP, CYCLONEIV, CYCLONEIV_HSSI, CYCLONEIV_PCIE_HIP, CYCLONEIVE, HARDCOPYIV_HSSI, HARDCOPYIV_PCIE_HIP, STRATIXV, STRATIXV_HSSI, STRATIXV_PCIE_HIP, ARRIAVGZ, ARRIAVGZ_HSSI, ARRIAVGZ_PCIE_HIP, ARRIAV, CYCLONEV.

The available Verilog libraries are ALTERA_MF_VER, ALTERA_VER, ALTERA_LNSIM_VER, LPM_VER, MAX_VER, MAXII_VER, MAXV_VER, STRATIX_VER, STRATIXII_VER, STRATIXIIGX_VER, ARRIAGX_VER, HARDCOPYII_VER, HARDCOPYIII_VER, HARDCOPYIV_VER, CYCLONE_VER, CYCLONEII_VER, CYCLONEIII_VER, CYCLONEIIILS_VER, SGATE_VER, STRATIXGX_VER, ALTGXB_VER, STRATIXGX_GXB_VER, STRATIXIIGX_HSSI_VER, ARRIAGX_HSSI_VER, ARRIAII_VER, ARRIAII_HSSI_VER, ARRIAII_PCIE_HIP_VER, ARRIAIIGZ_VER, ARRIAIIGZ_HSSI_VER, ARRIAIIGZ_PCIE_HIP_VER, STRATIXIII_VER, STRATIXIV_VER, STRATIXIV_HSSI_VER, STRATIXIV_PCIE_HIP_VER, STRATIXV_VER, STRATIXV_HSSI_VER, STRATIXV_PCIE_HIP_VER, ARRIAVGZ_VER, ARRIAVGZ_HSSI_VER, ARRIAVGZ_PCIE_HIP_VER, ARRIAV_VER, ARRIAV_HSSI_VER, ARRIAV_PCIE_HIP_VER, CYCLONEV_VER, CYCLONEV_HSSI_VER, CYCLONEV_PCIE_HIP_VER, CYCLONEIV_VER, CYCLONEIV_HSSI_VER, CYCLONEIV_PCIE_HIP_VER, CYCLONEIVE_VER, HARDCOPYIV_HSSI_VER, HARDCOPYIV_PCIE_HIP_VER.

Xilinx ISE/Vivado

Use the New DVT Project Wizard (menu File > New > DVT Project or DVT: Create a Project command in VS Code) to create a DVT project in the same location as an existing Xilinx ISE/Vivado project. All source files and settings defined in the ISE/Vivado project configuration files will be automatically recognized.

If you want to create a DVT project in a different location from your ISE/Vivado project location you must tune the .dvt/default.build file:

+dvt_init_auto
# Note that the compilation root must be specified after the +dvt_init_auto directive
+dvt_compilation_root+/xilinx/project/location

Note

ISE/Vivado projects are automatically recognized by the DVT build auto-configuration engine. For more details, see Auto-config. When the auto-configuration algorithm detects an ISE/Vivado project layout, it scans the existing ISE/Vivado project configuration files and automatically generates an equivalent DVT build configuration file (for example default.build.auto.1).

Note

The New DVT Project Wizard automatically adds both Verilog and VHDL natures. You can manually adjust this setting.

Note

For an ISE project, the required Xilinx libraries are automatically detected and compiled using the +dvt_init_xilinx directive in the generated auto build file. For a Vivado project, the required Xilinx libraries are NOT automatically detected and have to be manually specified. To manually specify the libraries, use the +dvt_init_xilinx directive in the project build configuration file:

+dvt_init_xilinx+UNISIM+UNIMACRO_VER
+dvt_setenv+DVT_XILINX_HOME=/apps/xilinx/Vivado/2014.2/

# Note that the +dvt_init_xilinx must be specified before the +dvt_init_auto directive
+dvt_init_auto

Xilinx ISE/Vivado Auto-config Specific Directives

Directive	Description
`+dvt_autoconfig_vivado_sim_fileset+<fileset_name>`	Auto-config from Vivado project using the <fileset_name> fileset.
`+dvt_autoconfig_ise_xise+<xise_file_name>`	Auto-config from ISE project using the <xise_file_name> file.
`+dvt_autoconfig_disable_xilinx`	Disables auto-config from Xilinx ISE/Vivado project. Fallback to default auto-config.

Xilinx Libraries Compilation

In order to compile Xilinx libraries:

specify the required libraries using the +dvt_init_xilinx directive
specify the Xilinx installation path (ISE or Vivado), unless $DVT_XILINX_HOME system variable is set

For example:

+dvt_init_xilinx+UNISIM+UNIMACRO_VER
+dvt_setenv+DVT_XILINX_HOME=/apps/xilinx/Vivado/2014.2/

The available libraries are UNISIM, UNIMACRO, UNIFAST, XILINXCORELIB, CPLD, SIMPRIM, SECUREIP_VER, UNISIMS_VER, UNIFAST_VER, UNIMACRO_VER, SIMPRIMS_VER, XILINXCORELIB_VER, UNI9000_VER, CPLD_VER, RETARGET, XPM.