All Build Directives

Note

GLOBAL directives are effective for all invocations. They are not reset by +dvt_init directives.

Directive	Note	Description
`-ams`		In dvt and vcs.vlogan compatibility modes: enables Verilog AMS 2.3 extended syntax for Verilog/SystemVerilog files. In questa.vlog compatibility mode: enables wreal extended syntax for Verilog/SystemVerilog files. In xcelium.xrun and ius.irun compatibility mode: all files that would be parsed with a Verilog / VHDL syntax flavor will be parsed with Verilog AMS 2.3 / VHDL AMS 1999 instead. Has precedence over other syntax specifications.
`-amscompilefile "file:<file_path>[ ...]"`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent with specifying <file_path> as a top file.
`-asext <ext>[,<ext>]`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `-as_ext +<ext>[,<ext>]`
`-CFLAGS` `-ccflags` `-ccargs` `-I -D -L -l -imacros -include`	GLOBAL	Gcc arguments used by DVT to configure the CDT builder.
`-ccext <ext>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `-c_ext +<ext>[,<ext>]`
`-cxxext <ext>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `-cpp_ext +<ext>[,<ext>]`
`-cuname <compilation_unit_name>`		Compile under <compilation_unit_name> package; the directive is enforced until: * another `-cuname` directive is encountered * `+dvt_init` directive is encountered * end of default.build is encountered
`-default_ext <syntax>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Set the Language Syntax for Unmapped Extensions. See xcelium.xrun Compatibility Mode or ius.irun Compatibility Mode for more details regarding the <syntax> argument.
`+define+<DEFINE_NAME>=<replacement>` `-define <DEFINE_NAME>=<replacement>`		Define a preprocessing symbol for SystemVerilog and e Langauge. Symbols defined using defineall are also available in C/C++. The replacement is optional. You may quote the replacement with ticks (’) or quotes (“). If defined, environment variables are expanded.
`+defineall+<DEFINE_NAME>=<replacement>` `-defineall <DEFINE_NAME>=<replacement>`		Same as `+define` / `-define`, except that the symbol is also defined for C/C++.
`+dvt_active_test+<path>`	e Language Only	The definition of structs/units/types declared in several Test Files is considered to be the one in the Active Test File.
`+dvt_auto_link+<true/false>`	GLOBAL	Enable automatic linking of resources located outside the project location. Default: true.
`+dvt_auto_snps_vip_macros`	GLOBAL	Generate and load in each invocation .dvt/auto_snps_vip_macros.svh file. It contains dummy definitions for macros which are commonly used but not defined or encrypted in Synopsis VIPs. The file will be overwritten if it already exists.
`+dvt_auto_snps_vip_waivers`	GLOBAL	Generate and load .dvt/auto_snps_vip_waivers.xml file. It contains waivers for problems commonly encountered when working with encrypted Synopsis VIPs. The file will be overwritten if it already exists.
`+dvt_encrypted_code_auto_close+<pattern>`	GLOBAL	Automatically close asymmetrically encrypted scopes such as missing endfunction/endtask, endclass, endpackage etc. in files matching the specified pattern. To disable automatic scope closing for particular files, use `+dvt_encrypted_code_auto_close+not+<pattern>`. Exclusion patterns are applied on top of inclusion patterns, regardless of specification order.
`+dvt_encrypted_code_auto_api+<pattern>`	GLOBAL	Automatically define missing API such as functions and fields referenced in files matching the specified pattern. API is defined in the closest eligible scope which has encrypted areas within its definition, for example the first class parent containing a \`protected ... \`endprotected section. If no such scope exists, auto-definition is not performed. To disable automatic definition of API referenced in particular files, use `+dvt_encrypted_code_auto_api+not+<pattern>`. Exclusion patterns are applied on top of inclusion patterns, regardless of specification order.
`+dvt_encrypted_code_auto_macro+<pattern>`	GLOBAL	Automatically define missing macros if the macro name matches the specified pattern.
`+dvt_auto_link_file+<path/to/file>`	GLOBAL	Auto-link the specified file.
`+dvt_auto_link_root+<alias>=<root_path>`	GLOBAL	When Auto-Linking <root_path>/subpath/to/file link it as DVT Auto-Linked/<alias>/subpath/to/file This directive helps to reduce the depth of the virtual filesystem hierarchy under DVT Auto-Linked, because the <root_path> sequence of virtual folders is compacted to <alias> virtual folder. The <root_paths> and <aliases> specified like this must be unique, and therefore only the first occurrence is considered. This is a global directive. Aliases may not be names of directories located directly under the filesystem root (like for example etc or bin).
`+dvt_auto_link_using_links+<true/false>`	GLOBAL	If set to false, an alternative mechanism is used for auto-linking files outside the project and paths won’t be serialized inside the ‘.project’ file. Requires a full build to take effect. (Experimental)
`+dvt_autoconfig_quartus_project_revision+<revision_name>`	SystemVerilog and VHDL only	Use <revision_name>.
`+dvt_autoconfig_debug`	GLOBAL	Enables printing of debug information. Use `+dvt_autoconfig_debug+SCAN` to see detailed scanning progress reported in the Console View. Use `+dvt_autoconfig_debug+SORT` to see detailed information about file ordering in Console View
`+dvt_autoconfig_disable_quartus`	SystemVerilog and VHDL only	Ignore Quartus project configuration files and fallback to default auto-config.
`+dvt_autoconfig_disable_xilinx`	SystemVerilog and VHDL only	Disables auto-config from Xilinx ISE/Vivado project. Fallback to default auto-config.
`+dvt_autoconfig_ise_xise+<xise_file_name>`	SystemVerilog and VHDL only	Auto-config from ISE project using the <xise_file_name> file.
`+dvt_autoconfig_quartus_script_location+<script_file_path>`	SystemVerilog and VHDL only	For debugging purposes. Use <script_file_path> to analyze Quartus project configuration files.
`+dvt_autoconfig_timeout+<timeout_seconds>`		Interrupt build if project autoconfiguration takes more than the specified threshold (in seconds). Set 0 to disable timeout. Default: 40 seconds.
`+dvt_autoconfig_follow_symlinks+<max_nested>`	GLOBAL	Auto-config scan will descend into symlinks, up to the specified max number of nested symlinks. Set 0 to not descend into symlinks.
`+dvt_autoconfig_vivado_sim_fileset+<fileset_name>`	SystemVerilog and VHDL only	Auto-config from Vivado project using the <fileset_name> fileset.
`+dvt_simlog_pattern+<pattern>`	SystemVerilog and VHDL only	Specify a regular expressions pattern to be searched in the simulator log. Must contain a capturing group with the name ‘args’. The string matched by this group will be copied to the resulting `+dvt_init` section.
`+dvt_simlog_buffer_max_size+<size in MB>`	SystemVerilog and VHDL only	Specify the maximum size of the buffer that will be read from the simulator log file, in MB.
`+dvt_simlog_timeout+<seconds>`	SystemVerilog and VHDL only	Interrupt build if project configuration from simulator log takes more than the specified threshold (in seconds), by default after 10 seconds. Set 0 to disable timeout.
`+dvt_simlog_full_scan+<true/false>`	SystemVerilog and VHDL only	Specify if the entire simulator log file should be scanned and all invocations should be extracted.
`+dvt_build_log_file_location+<path_to_existing_directory>`	GLOBAL	Specify the location of the internal builder log file. Default: ./ (Project location).
`+dvt_build_log_to_console+<true/false>`	GLOBAL	Enable/disable internal builder logging to console. Default: true.
`+dvt_build_log_to_file+<true/false>`	GLOBAL	Enable/disable internal builder logging to file. Default: true.
`+dvt_cpf+<cpf_file>`	SystemVerilog and VHDL Only	Specify a CPF file for compilation.
`+dvt_cdt_file_type_auto_map+SYSTEM_HEADERS` `+dvt_cdt_file_type_auto_map+DISABLE`	C/C++ only	By default DVT automatically configures top files as C++ source files and included files as C++ header files. Using `+dvt_cdt_file_type_auto_map+SYSTEM_HEADERS` instructs DVT to configure only included system headers as C++ header files. Using `+dvt_cdt_file_type_auto_map+DISABLE` instructs DVT to use the default CDT file types.
`+dvt_cdt_file_type_map+<CDT_file_type>+<name_or_ext>`	C/C++ only	Specify the CDT file type for a filename or file extension. <CDT_file_type> can be one of CPP_SOURCE, CPP_HEADER, C_SOURCE, C_HEADER <name_or_ext> is interpreted as file extension if it starts with a dot (for example .cpp) or a filename otherwise.
`+dvt_compilation_root+</path/to/compilation/root>`		Specify the compilation root. Relative paths specified in default.build will be resolved as relative to this location, except for the special cases that rise when Including Other Argument Files.
`+dvt_autoconfig_scan_root_add+<path1>+<path2>+...` `+dvt_autoconfig_scan_root_clear`		By default, all source files in the compilation root directory are scanned, recursively. Use `+dvt_autoconfig_scan_root_add` to specify additional directories to be scanned. Specify `+dvt_autoconfig_scan_root_clear` to clear the list of scan dirs.
`+dvt_compile_waivers_file+<path>`	GLOBAL	Specify a compile waivers file.
`+dvt_db_location+<path>`	GLOBAL	Save the project database files under: - DVT Eclipse: <path>/dvt_db/<project_name> - DVT for VS Code: <path> The directory will be created if needed and may be overwritten at each full/incremental project build. For DVT Eclipse, in certain situations (for example if write access for <path>/dvt_db/<project_name> is denied or the directory is in use by another DVT instance) DVT falls back to the default location: <dvt_workspace>/.metadata/.plugins/org.eclipse.core.resources/.projects/<project_name>. For DVT for VS Code, in certain situations (for example if write access for <path> is denied or the directory is locked by another Language Server) DVT will build the project from scratch.
`+dvt_usage_before_declaration_check+<scope>`	GLOBAL	Control the context in which USAGE_BEFORE_DECLARATION errors are being reported. As a general rule, files compiled with wildcards or auto-configured via `+dvt_init_auto` will not generate any of these errors. Valid scopes are: ALL - error always reported INVOCATION (default) - errors reported only if usage and declaration are in the same invocation (same +dvt_init) FILE - errors reported only if usage and declaration are in the same file NONE - errors are never reported
`+dvt_define_system_function+<function1_name>+<function2_name>+...`	SystemVerilog Only	Define System Verilog system functions with the provided names.
`+dvt_define_system_task+<task1_name>+<task2_name>+...`	SystemVerilog Only	Define System Verilog system tasks with the provided names.
`+dvt_disable_parallel_lex_parse`	GLOBAL SystemVerilog Only	Disable lexing-parsing parallelization.
`+dvt_disable_preproc_optimize+<true/false>`	GLOBAL SystemVerilog Only	Disable DVT preprocessing optimizations. Default: false.
`+dvt_disable_rtl_checks`	GLOBAL SystemVerilog and VHDL Only	Disable the RTL specific semantic checks: SENSITIVITY_MISSING/SENSITIVITY_UNUSED and SIGNAL_NEVER_READ/SIGNAL_NEVER_WRITTEN/SIGNAL_NEVER_USED. By default the checks are enabled.
`+dvt_disable_checks+<check_id1>+<...>`	GLOBAL SystemVerilog and VHDL Only	Disable a set of semantic checks by ID.For example: `+dvt_disable_checks+REDUNDANT_OTHERS_CHOICE` Possible check IDs: REDUNDANT_OTHERS_CHOICE, MISSING_OTHERS_CHOICE, ELABORATION_WIDTH_MISMATCH. By default no checks are disabled.
`+dvt_disable_uvm_reuse`	GLOBAL SystemVerilog Only	Compile the UVM package in every invocation which specifies `-uvm` / `-ntb_opts uvm`. By default UVM is compiled only in the first invocation, and subsequent `-uvm` / `-ntb_opts uvm` only provide the UVM incdir. Default value: false
`+dvt_disable_naming_convention_checks`	GLOBAL e Language and VHDL Only	Disable naming convention checks. Default value: false
`+dvt_disable_nontop_files_compilation`	GLOBAL	Disable compilation of non-top files. Non-top files are files which are not part of the full compilation. Default value: false
`+dvt_e_enable_non_standard_checks+<true/false>`	GLOBAL e Language Only	Enable/disable non-standard syntax and semantic checks. Default: false.
`+dvt_strict_non_standard_checks+<true/false>`	GLOBAL	Enable/disable strict non-standard checking. Default: false.
`+dvt_e_skip_incr_dep+<pattern>`	GLOBAL e Language Only	During incremental build, semantic checks are performed in the changed file and in all files that depend on it. Use this directive to skip analysis of dependent files that match the specified pattern. Use multiple times to specify multiple patterns. A pattern can use the wildcards * (any character sequence) and ? (any character).
`+dvt_e_sn_which_emulation`	GLOBAL e Language Only	Use the following set of search paths to locate VIPs instead of sn_which.sh:/ <IUS Install Location>/specman/linux/ <IUS Install Location>/specman/src/ <IUS Install Location>/specman/docs/ <IUS Install Location>/specman/tcl/specman/ <IUS Install Location>/specman/linux/ <IUS Install Location>/specman/src/ <IUS Install Location>/specman/docs/ <IUS Install Location>/specman/tcl/specman/ <IUS Install Location>/specman/erm_lib/ <IUS Install Location>/specman/sn_lib/ <IUS Install Location>/specman/packages/ <IUS Install Location>/specman/uvm/uvm_lib/ <IUS Install Location>/specman/ovm/ovm_lib/ <IUS Install Location>/specman/erm_lib/ <IUS Install Location>/specman/sn_lib/ <IUS Install Location>/specman/packages/ <IUS Install Location>/specman/uvm/uvm_lib/ <IUS Install Location>/specman/ovm/ovm_lib/
`+dvt_e_macro_strict_exp_checking+<true/false>`	GLOBAL e Language Only	If true, the <exp> match expression will match only valid expressions. If false, <exp> is equivalent with the <any> match expression that matches any non-empty sequence of characters. Default: false.
`+dvt_e_macro_exp_back_tracking+<true/false>`	GLOBAL e Language Only	If true, the parser will reject a user defined expression match if the result of the macro reparse is not a valid expression. Default: true.
`+dvt_e_sn_extract_defines+<true/false>`	GLOBAL e Language Only	Automatically extract and define the Specman version defines. Default: true.
`+dvt_e_sn_which_add+<vip1>+<vip2>+...` `+dvt_e_sn_which_clear`	GLOBAL e Language Only	By default, the following VIPs are located using sn_which.sh, and their locations are added to the $SPECMAN_PATH: evc_util, vr_ad, uvm_e. Use `+dvt_sn_which_add+<vip1>+<vip2>+...` to add to this list and `+dvt_sn_which_clear` to clear it.
`+dvt_e_vtop+"pkg_name::SUBTYPE unit_name"`	e Language Only	Specify a verification top unit. Subtype and package name are optional. Quotes are mandatory when specifying a subtype. Multiple top units may be specified.
`+dvt_editor_association_override+<pattern>=<editor>`	GLOBAL	Open files matching <pattern> with specified <editor>. This directive overrides Eclipse editor association preferences. The <editor> is either one of (SV, VHDL, E, SLN, PSS, SDL, BC, CPP, BASH, JAVA, LUA, PERL, PYTHON, RUBY, TCL), the full path to an executable, the name of executable found in $PATH, or a valid Eclipse editor ID. The <pattern> is matched against the file’s full path and can use ‘*’ (any char sequence) and ‘?’ (any character) wildcards.
`+dvt_enable_elaboration_incremental+<NONE/ADAPTIVE/FULL>`	GLOBAL SystemVerilog and VHDL Only	Configure the type of elaboration performed after an incremental build. `+dvt_enable_elaboration_incremental+NONE` - no elaboration is performed. The design hierarchy and design problems can become obsolete. `+dvt_enable_elaboration_incremental+ADAPTIVE` - based on the incremental delta, only relevant parts of the design hierarchy are reevaluated. If the changes are too great, a notification appears that asks for FULL elaboration. `+dvt_enable_elaboration_incremental+FULL` - the full elaboration of the design is performed. To be used only when the increase in the incremental duration is acceptable. Default: ADAPTIVE.
`+dvt_enable_elaboration_empty_tops+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Enable elaboration of a top module without any local instances or generate blocks. Default: false.
`+dvt_elaboration_skip_modules+<simple_pattern>`	GLOBAL SystemVerilog and VHDL Only	Skip elaboration of an instance whose design name matches the specified <simple_pattern>. Wildcards such as ‘’ (any string) and ‘?’ (any character) can be used in the pattern. Instance port connections and parameter overrides are checked but sub-instances are not elaborated. Skipped designs are considered unelaborated*. Elaboration tops cannot be skipped.
`+dvt_elaboration_skip_modules+not+<simple_pattern>`	GLOBAL SystemVerilog and VHDL Only	Skip elaboration of an instance whose design name does not match the specified <simple_pattern>. Wildcards such as ‘’ (any string) and ‘?’ (any character) can be used in the pattern. Instance port connections and parameter overrides are checked but sub-instances are not elaborated. Skipped designs are considered unelaborated*. Elaboration tops cannot be skipped.
`+dvt_elaboration_skip_paths+<simple_pattern>`	GLOBAL SystemVerilog and VHDL Only	Skip elaboration of an instance whose design file absolute path matches the specified <simple_pattern>. Wildcards such as ‘’ (any string) and ‘?’ (any character) can be used in the pattern. Instance port connections and parameter overrides are checked but sub-instances are not elaborated. Skipped designs are considered unelaborated*. Elaboration tops cannot be skipped.
`+dvt_elaboration_skip_paths+not+<simple_pattern>`	GLOBAL SystemVerilog and VHDL Only	Skip elaboration of an instance whose design file absolute path does not match the specified <simple_pattern>. Wildcards such as ‘’ (any string) and ‘?’ (any character) can be used in the pattern. Instance port connections and parameter overrides are checked but sub-instances are not elaborated. Skipped designs are considered unelaborated*. Elaboration tops cannot be skipped.
`+dvt_elaboration_skip_instances+<simple_pattern>`	GLOBAL SystemVerilog and VHDL Only	Skip elaboration of an instance whose hierarchical path matches the specified <simple_pattern>. Wildcards such as ‘’ (any string) and ‘?’ (any character) can be used in the pattern. Instance port connections and parameter overrides are checked but sub-instances are not elaborated. Skipped designs are considered unelaborated*. Elaboration tops cannot be skipped.
`+dvt_elaboration_skip_instances+not+<simple_pattern>`	GLOBAL SystemVerilog and VHDL Only	Skip elaboration of an instance whose hierarchical path does not match the specified <simple_pattern>. Wildcards such as ‘’ (any string) and ‘?’ (any character) can be used in the pattern. Instance port connections and parameter overrides are checked but sub-instances are not elaborated. Skipped designs are considered unelaborated*. Elaboration tops cannot be skipped.
`+dvt_elaboration_skip_defparams+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Skip defparam assignments during elaboration. Default: false.
`+dvt_elaboration_filter_width_mismatch+<true/false>`	GLOBAL SystemVerilog Only	Filter width mismatch warnings in the following cases: right-hand side assignment operators, UVM/OVM field automation macros, ‘uvm_bitstream_t’ operands, truncation and padding safe decimal numbers. Default: true.
`+dvt_elaboration_control+<EACH_GENERATE_BLOCK_ONCE/NO_GENERATE_BLOCKS/NO_PARAM_EVAL>`	GLOBAL SystemVerilog and VHDL Only	Disable or change steps in the elaboration. Use EACH_GENERATE_BLOCK_ONCE to elaborate each generate block, whether active or inactive, only once. Use NO_GENERATE_BLOCKS to not elaborate generate blocks. Use NO_PARAM_EVAL to disable parameter evaluation.
`+dvt_elaboration_max_recurrence_depth+<maxValue>`	GLOBAL SystemVerilog and VHDL Only	Configure the maximum recurrence depth for instances under generate blocks. Default: 5.
`+dvt_elaboration_max_nof_resolve_binds_passes+<maxValue>`	GLOBAL SystemVerilog and VHDL Only	Configure the maximum number of passes allowed when resolving bind directives. Default: 5.
`+dvt_elaboration_loop_block_cutoff+<maxValue>`	GLOBAL SystemVerilog and VHDL Only	Configure the cut-off number for elaborated loop generate blocks. Default: 200.
`+dvt_elaboration_loop_statement_cutoff+<maxValue>`	GLOBAL SystemVerilog and VHDL Only	Configure the cut-off number for elaborated function loop statements. Default: 1000.
`+dvt_elaboration_liblist+<lib1>[+<lib2>+...]`	GLOBAL SystemVerilog and VHDL Only.	When solving references to modules or entities which are not defined in the current library, DVT tries to resolve them in other compiled libraries according to: -the order specified by liblist clauses of verilog configuration -the order specified by this directive -compilation order
`+dvt_unelaborated_compile_checks+<NONE/GENERATE_BLOCKS/DISCRETE/FULL>`	GLOBAL SystemVerilog and VHDL Only	In order to speed-up full compilation, you can choose to restrict functionality and checking in the unelaborated part of the design. This directive controls the scope of the unelaborated design build checks and functionality: `+dvt_unelaborated_compile_checks+NONE` - functionality and checking in the unelaborated modules and unelaborated local generate blocks is limited. `+dvt_unelaborated_compile_checks+GENERATE_BLOCKS` - functionality and checking in all unelaborated modules is limited. `+dvt_unelaborated_compile_checks+DISCRETE` - functionality and checking in the unelaborated modules found in library files is limited. `+dvt_unelaborated_compile_checks+FULL` - functionality and checking is not limited in the unelaborated code. Default: DISCRETE.
`+dvt_unelaborated_disable_package_constants+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Disable unelaborated package constants evaluation and checking. Default: false.
`+dvt_defparam+<top_module_name>.<sub_instance1>.<sub_instance2>.. <sub_instanceN>.<parameter_name>=<override_value>`	GLOBAL SystemVerilog Only	Overrides the parameter ‘parameter_name’ at hierarchy path ‘top_module.sub_instance1…sub_instanceN’ with ‘override_value’. Works similar to SystemVerilog defparam statement, but has a higher priority and can also override localparams. Expressions are NOT allowed for override, only simple integer and string values!
`+dvt_enable_unknown_directive_warnings+<true/false>`	GLOBAL	Trigger warnings for unknown build directives. Default: false.
`+dvt_ext_map+<syntax>+<ext>`		Files with <ext> extension are parsed using the specified <syntax>. See Default DVT Compatibility Mode for more details regarding <syntax>.
`+dvt_ext_unmap+<ext>`		Files with <ext> extension are parsed using the Language Syntax for Unmapped Extensions.
`+dvt_ext_unmap_all`		All files are parsed using the Language Syntax for Unmapped Extensions.
`+dvt_ext_unmapped_syntax+<syntax>`		Set the Language Syntax for Unmapped Extensions. See Default DVT Compatibility Mode for more details regarding <syntax>.
`+dvt_extract_comment_above+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Extract comments above elements. Default: true.
`+dvt_extract_comment_above_max_empty_lines+<number_of_lines>`	GLOBAL SystemVerilog and VHDL Only	Extract comment if located at no more than specified number of empty lines above element declaration. Default: 1.
`+dvt_extract_comment_bcd+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Extract / begin comment delimiter comments. Default:** true.
`+dvt_extract_comment_header+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Extract file header comments and associate them with the first element in file (module, entity etc.). Default: false.
`+dvt_extract_comment_inline+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Exctract comments inline with elements. Default: true.
`+dvt_extract_comment_ml+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Extract /* multi line comments. Default: true.
`+dvt_extract_comment_sl+<true/false>`	GLOBAL SystemVerilog and VHDL Only	Extract // single line comments. Default: true.
`+dvt_file_compile_timeout+<timeout>`	GLOBAL	During full compilation, skip parsing the entire invocation if a file takes more than the specified threshold (in seconds). Set 0 to disable timeout. Default: 40 seconds.
`+dvt_file_substitute+<file_path>=<substitute_file_path>`	GLOBAL	During compilation, the <file_path> file will be substituted with the <substitute_file_path> file. Works both for source files and included build configuration files.
`+dvt_full_compile_checks+<scope>`	GLOBAL SystemVerilog and VHDL Only	In order to speed-up full compilation, you may chose to fully check only a relevant subset of your source code. This directive controls the scope of the full build checks: `+dvt_full_compile_checks+FULL` - all of the code is checked `+dvt_full_compile_checks+LIBS+lib1+lib2` - only the specified libraries are checked, some basic checks are still performed for the rest of the code `+dvt_full_compile_checks+NOT_LIBS+lib1+lib2` - all of the code is checked except for the specified libraries, where only some basic checks are performed `+dvt_full_compile_checks+PKGS+lib1::pkg1+lib2::pkg2` - only the specified packages are checked, some basic checks are still performed for the rest of the code `+dvt_full_compile_checks+NOT_PKGS+lib1::pkg1+lib2::pkg2` - all of the code is checked except for the specified packages, where only some basic checks are performed `+dvt_full_compile_checks+OFF` - only some basic checks are performed Default: FULL
`+dvt_gcc+</path/to/gcc_executable>`	GLOBAL	Specify location of GCC executable (used when scanning for included C/C++ files and injected in the CDT project configuration).
`+dvt_gcc_args+"args string"`	GLOBAL	Specify extra arguments for the GCC executable (used when scanning for included C/C++ files and injected in the CDT project configuration).
`+dvt_gcc_timeout+<timeout>`	GLOBAL	Timeout in seconds when running GCC. Set 0 to disable timeout. Default: 40 seconds.
`+dvt_hdtv`	GLOBAL SystemVerilog Only	Hide duplicates from Types, Checks and Coverage Views.
`+dvt_incremental_compile_checks+<scope>`	GLOBAL SystemVerilog and VHDL Only	In order to speed-up incremental compilation, you may chose to turn off advanced checking. `+dvt_incremental_compile_checks+OFF` - only some basic checks are performed all over the code `+dvt_incremental_compile_checks+ON` - checks are performed in all affected areas of your code that are also checked at full build (see `+dvt_full_compile_checks`) Default: ON Note if +dvt_full_compile_checks is set to OFF this flag has no effect.
`+dvt_incremental_compile_max_lines+<max_lines_number>`	GLOBAL	Files with more than max lines will not be incrementally compiled. Set 0 for infinite limit. Default: 15000.
`+dvt_incremental_compile_timeout+<timeout>`	GLOBAL	During incremental compilation, skip the file if parsing or semantic checking takes more than the specified threshold (in seconds). When incremental build is performed on multiple files, the semantic checking timeout is increased proportionally (1 second for every 2 files). Set 0 to disable timeout. Default: 4 seconds.
`+dvt_init[+<compat_mode>]`		Equivalent of a new invocation, resets all directives except for the GLOBAL ones. See Compatibility Modes for a detailed description.
`+dvt_init_auto[+<compat_mode>]`		Automatically identify and compile all the source files in the compilation root. The compilation root defaults to the project directory and can be changed using `+dvt_compilation_root+` directive. If a compatibility mode is not specified, it defaults to dvt. See Auto-config for a detailed description.
`+dvt_init_altera[+<lib1>+<lib2+...>]`		Compile the specified libraries from the $QUARTUS_ROOTDIR installation. Similar with `+dvt_init`, it is equivalent with a new invocation. See Intel(Altera) Quartus Libraries Compilation for a detailed description.
`+dvt_init_xilinx[+<lib1>+<lib2+...>]`		Compile the specified libraries from the $DVT_XILINX_HOME installation. Similar with `+dvt_init`, it is equivalent with a new invocation. The available libraries are UNISIM, UNIMACRO, UNIFAST, XILINXCORELIB, CPLD, SIMPRIM, SECUREIP_VER, UNISIMS_VER, UNIFAST_VER, UNIMACRO_VER, SIMPRIMS_VER, XILINXCORELIB_VER, UNI9000_VER, CPLD_VER, RETARGET. See Xilinx Libraries Compilation for a detailed description.
`+dvt_init_from_simlog[+<compat_mode>+<simulation_logfile>]`		Compile using arguments extracted from the provided simulator log file.The simulator which generated the logfile is detected from its content, unless a compatibility mode is specified: ius.irun, xcelium.xrun, vcs.vlogan, vcs.vhdlan, questa.vsim and questa.vcom. See Simulator Log-config for a detailed description.
`+dvt_init_questa_libs[+<lib1>+<lib2+...>]`		Compile the specified libraries from the `$MTI_HOME` installation. Similar with `+dvt_init`, it is equivalent with a new invocation. The available VHDL libraries are: MODELSIM_LIB. See Questa Libraries Compilation for a detailed description.
`+dvt_init_uvvm`		Compile the UVVM sources. Similar with `+dvt_init`, it is equivalent with a new invocation.
`+dvt_init_uuvm_vvc`		Compile the UVVM_VVC sources. It should be used for every VVC. Similar with `+dvt_init`, it is equivalent with a new invocation.
`+dvt_init_osvvm`		Compile the OSVVM sources. Similar with `+dvt_init`, it is equivalent with a new invocation.
`+dvt_init_precompiled_db_load`	SystemVerilog Only	Load a precompiled library. Similar with `+dvt_init`, it is equivalent with a new invocation. See also Precompilation Support.
`+dvt_max_nof_threads+<num_threads>`	GLOBAL	Configure the maximum number of threads to use during different phases of intensive computation (e.g. semantic checking, etc.). Default: 8
`+dvt_documentation_resource_locations_add+<location>`	GLOBAL	Specify additional search locations for the NaturalDocs and JavaDoc link tags.
`+dvt_path_pattern_timeout+<timeout>`		Timeout in seconds when scanning path patterns (like for example /*/.v). Default: 5.
`+dvt_path_pattern_sorting_timeout<timeout>`		Timeout in seconds when sorting files specified using path pattern wildcards. Default: 5.
`+dvt_pf_debug`	SystemVerilog and VHDL Only	Print debug information during power format build phase.
`+dvt_prepend_init`	GLOBAL	You can use a `+dvt_prepend_init` section to specify directives like `+define`, `+dvt_setenv`, `+incdir` etc. that are prepended to all `+dvt_init` sections. All directives between `+dvt_prepend_init` and the next `+dvt_init` will be “copied” in all subsequent `+dvt_init` sections. Note The +dvt_prepend_init directive must be in the same file as the next +dvt_init directive.
`+dvt_preprocess_translate_pragmas+<pragma1>+<pragma2>+...`	SystemVerilog Only	Instructs DVT to skip analyzing the code between pragmas such as // <pragma> translate_off // <pragma> translate_on You can specify any number of pragmas as arguments to this directive, separated by ‘+’ like for example `+dvt_preprocess_translate_pragmas+pragma+synopsys+synthesis` Note In VHDL, the code background will be highlighted, but it will still be analyzed.
`+dvt_profile+<name>+<interval>`	SystemVerilog and VHDL Only	Instruct DVT to collect thread dumps for specific named actions that the tool performs. The interval between thread dumps can also be specified as the last argument of the directive, in milliseconds. If not specified, the interval defaults to 500ms.
`+dvt_profile_incremental+<threshold>+<interval>`	SystemVerilog and VHDL Only	Instruct DVT to collect thread dumps if incremental compilation takes more than <threshold> milliseconds. The interval between thread dumps is <interval> milliseconds. If not specified, the interval defaults to 500ms, and the threshold to 2 seconds.
`+dvt_profile_parser+<simple_pattern>`	SystemVerilog, VHDL and PSS Only	Collect thread dumps during parsing for file full paths that match the specified pattern. Use `+dvt_profile_parser_add+<simple_pattern>` to specify additional file paths. Use `+dvt_profile_parser_clear` to clear the list of file paths. A pattern can use the wildcards * (any character sequence) and ? (any character).
`+dvt_pss_cpp`		Add $PSS_CPP_HOME/include/pss.h as topfile and $PSS_CPP_HOME/include as C include dir. Falls back to `$DVT_PSS_CPP_HOME` if `$PSS_CPP_HOME` is not defined. Falls back to $DVT_HOME/predefined_projects/libs/pss-cpp_v2018.05.16 if `$DVT_PSS_CPP_HOME` is not defined.
`+dvt_pverilog_comment_map+"<regex_pattern>"`	GLOBAL SystemVerilog Only	Infer mapping from generated files, assuming they contain a comment pointing to the corresponding PVerilog source file. Specify a regular expression pattern containing a named capturing group called PFILE. The pattern is applied to all comments at full build time. For example: `+dvt_pverilog_comment_map+"Source file: (?<PFILE>\S+)"`
`+dvt_pverilog_comment_map_debug`	GLOBAL SystemVerilog Only	Turn on debugging for `+dvt_pverilog_comment_map`. Pattern match information will be printed in the build console. You can also specify a string to test the patterns against. For example: `+dvt_pverilog_comment_map_debug+"Source file: /path/to/file.vp"`
`+dvt_pverilog_compile_preproc`	GLOBAL SystemVerilog Only	Enable all the advanced navigation and editing features for the pure Verilog/SystemVerilog code from the PVerilog files.
`+dvt_pverilog_ext_map+<(p) files extension>=<(g) files extension>`	GLOBAL SystemVerilog Only	Map extensions of PVerilog files to extensions of generated Verilog files. For example: `+dvt_pverilog_ext_map+.svp=.sv`
`+dvt_pverilog_map+<(p) file path>=<(g) file path>`	GLOBAL SystemVerilog Only	Map a PVerilog file to the generated Verilog file. For example: `+dvt_pverilog_map+$SOURCE/file.svp=$GENERATED/file.sv`
`+dvt_pverilog_path_map+<path prefix of (p) files>=<path prefix of (g) files>`	GLOBAL SystemVerilog Only	Map root path of PVerilog files to root path of generated Verilog files. For example: `+dvt_pverilog_path_map+${PREPROCESS_SOURCE}=${PREPROCESS_TARGET}`
`+dvt_pverilog_pattern_tag_map+<(p) pattern1>=<(g) pattern2>`	GLOBAL SystemVerilog Only	Map a pattern of PVerilog files to another pattern of generated Verilog files. For example: `+dvt_pverilog_pattern_tag_map+<tag>.svp=<tag>_suffix.sv`
`+dvt_pverilog_run_on_save+"RUN_CONFIG_NAME"`	GLOBAL SystemVerilog Only	Specify the name of the run configuration to be executed when you save the PVerilog file in the PVerilog editor [p] or [c] tabs. Within the run configuration, use `${selected_resource_loc}` variable to refer to the path of the PVerilog file.
`+dvt_pverilog_scan_location_add+<path1>+<path2>+...` `+dvt_pverilog_scan_location_clear`	GLOBAL SystemVerilog Only	By default, in order to find the suitable PVerilog files for `+dvt_pverilog_ext_map` and `+dvt_pverilog_pattern_tag_map`, all source files located inside the project are scanned, recursively. Use `+dvt_pverilog_scan_location_add` to specify additional directories to be scanned. Specify `+dvt_pverilog_scan_location_clear` to clear the list of scan locations.
`+dvt_run_codan+FULL+INCR`	GLOBAL	Specify when CDT Codan analysis should be performed: FULL - at full build, INCR - at incremental build (for example when saving a file). By default Codan is disabled.
`+dvt_set_directive_nof_args+<directive_name>=<nof_args>`	GLOBAL	When encountering -directive_name, the following nof_args tokens are considered arguments of the directive.
`+dvt_semantic_checks_timeout+<timeout>`	GLOBAL SystemVerilog and VHDL Only	Popup semantic checking dialog asking to continue or stop when full compilation semantic checking takes more than the specified timeout (in seconds). Default value: 30.
`+dvt_setenv+<NAME>[=VALUE]`		Define an environment variable. The value is optional. Its value is visible for subsequent directives and during parsing. The environment variable is cleared by the next `+dvt_init+` directive. If the variable is already defined in the underlying shell or by previous directives, it will be overridden.
`+dvt_setenv_no_override+<NAME>[=VALUE]`		Define an environment variable. The value is optional. Its value is visible for subsequent directives and during parsing. The environment variable is cleared by the next `+dvt_init+` directive. If the variable is already defined in the underlying shell or by previous directives, it will not be overridden.
`+dvt_skip_compile+<simple_pattern>`		Instructs DVT to skip analyzing the files whose absolute path matches the specified <simple_pattern>. In a simple pattern you can use wildcards such as ‘*’ (any string) and ‘?’ (any character). Such skipped files are decorated distinctively in the Navigator View / Explorer View: DVT Eclipse: DVT for VS Code: See also Compilation Speed-up.
`+dvt_skip_compile+not+<simple_pattern>`		Instructs DVT to skip analyzing the files whose absolute path does not match the specified <simple_pattern>. In a simple pattern you can use wildcards such as ‘*’ (any string) and ‘?’ (any character). Such skipped files are decorated distinctively in the Navigator View / Explorer View: DVT Eclipse: DVT for VS Code: See also Compilation Speed-up.
`+dvt_skip_compile+regex+<regex_pattern>`		Instructs DVT to skip analyzing the files whose absolute path matches the specified <regex_pattern>. Such skipped files are decorated distinctively in the Navigator View / Explorer View: DVT Eclipse: DVT for VS Code: See also Compilation Speed-up.
`+dvt_skip_compile+regex+not+<regex_pattern>`		Instructs DVT to skip analyzing the files whose absolute path does not match the specified <regex_pattern>. Such skipped files are decorated distinctively in the Navigator View / Explorer View: DVT Eclipse: DVT for VS Code: See also Compilation Speed-up.
`+dvt_shallow_compile+<simple_pattern>`		Instructs DVT to shallow compile the files whose absolute path matches the specified <simple_pattern>. In a simple pattern you can use wildcards such as ‘’ (any string) and ‘?’ (any character). Such files are marked with [S]* in the Compile Order View and other views. In shallow compiled code, only parameters and ports are collected from modules and only arguments are collected from functions and tasks. See also Compilation Speed-up.
`+dvt_shallow_compile+not+<simple_pattern>`		Instructs DVT to shallow compile the files whose absolute path does not match the specified <simple_pattern>. In a simple pattern you can use wildcards such as ‘’ (any string) and ‘?’ (any character). Such files are marked with [S]* in the Compile Order View and other views. In shallow compiled code, only parameters and ports are collected from modules and only arguments are collected from functions and tasks. See also Compilation Speed-up.
`+dvt_shallow_compile+regex+<regex_pattern>`		Instructs DVT to shallow compile the files whose absolute path matches the specified <regex_pattern>. Such files are marked with [S] in the Compile Order View and other views. In shallow compiled code, only parameters and ports are collected from modules and only arguments are collected from functions and tasks. See also Compilation Speed-up.
`+dvt_shallow_compile+regex+not+<regex_pattern>`		Instructs DVT to shallow compile the files whose absolute path does not match the specified <regex_pattern>. Such files are marked with [S] in the Compile Order View and other views. In shallow compiled code, only parameters and ports are collected from modules and only arguments are collected from functions and tasks. See also Compilation Speed-up.
`+dvt_shallow_compile+<mode>`		Instructs DVT to shallow compile all elements definitions that match the given mode. In shallow compiled code, only parameters and ports are collected from modules and only arguments are collected from functions and tasks. Available modes are: ALL_MODULES, ALL_FUNCTIONS, ALL_TASKS. See also Compilation Speed-up.
`+dvt_precompiled_db_save+<path>`	SystemVerilog Only	Instructs DVT to save the dictionary as a precompiled database in the specified directory. See also Precompilation Support.
`+dvt_precompiled_db_location+<path>`	SystemVerilog Only	Specify the directory where the precompiled database should be loaded from. See also Precompilation Support.
`+dvt_precompiled_db_build_cmd+"<command>"`	SystemVerilog Only	Specify the build command to use when re-build of the precompiled database is required (DVT version change, precompiled files changed, etc.). See also Precompilation Support.
`+dvt_precompiled_db_disable_md5_change_detection`	SystemVerilog Only	Disables MD5 checksum change detection for precompiled files. See also Precompilation Support.
`+dvt_skip_directive+"<simple pattern>"`		Skip subsequent directives matching the specified pattern. You can specify this directive multiple times. A pattern can use the wildcards * (any character sequence) and ? (any character). The directive has effect for all subsequent directives in the same invocation. Note Does not apply to the +dvt_init directive. Note Any whitespace within directives is compacted to a single space character.
`+dvt_skip_ext+<ext>`		Do not parse top files with <ext> extension. The dot (.) for specifying <ext> is optional. For example `+dvt_skip_ext+.gv` and `+dvt_skip_ext+gv` are equivalent.
`+dvt_skip_protected_code+true`	GLOBAL SystemVerilog Only	Do not analyze code enclosed in \`protect ... \`endprotect pragmas.
`+dvt_systemc`		Add $SYSTEMC_HOME/src/systemc.h as topfile and $SYSTEMC_HOME/src as C include dir. Falls back to `$DVT_SYSTEMC_HOME` if `$SYSTEMC_HOME` is not defined. Falls back to $DVT_HOME/predefined_projects/libs/systemc-2.3.1a if `$DVT_SYSTEMC_HOME` is not defined.
`+dvt_test+<path>`	e Language Only	Specify a top file and mark it as test. For example, the e Language test files have a special status..
`+dvt_upf+<upf_file>`	SystemVerilog and VHDL Only	Specify a UPF file for compilation.
`+dvt_upf_std_defs+<version>`	SystemVerilog and VHDL Only	Compile HDL UPF packages for the specified version. Available versions are: 3.0 and 2.2. Default value: 3.0
`+dvt_undefine+<DEFINE_NAME>`	SystemVerilog Only	Undefines <DEFINE_NAME> preprocessing symbol. Equivalent with \`undef <DEFINE_NAME>. The `+dvt_undefine` directives are applied on top of all other specified `+defines`. Ordering relative to other specified top files is relevant.
`+dvt_wavedrom_file_ext_add+<extension>`	GLOBAL	Specify additional file extensions for the WaveDrom plugin.
`+dvt_wavedrom_file_ext_clear`	GLOBAL	Clear the extensions list for the WaveDrom plugin.
`+dvt_wavedrom_files_location_add+<location>`	GLOBAL	Specify additional search file locations for the WaveDrom plugin.
`+dvt_wavedrom_files_location_clear`	GLOBAL	Clear the search file locations list for the WaveDrom plugin.
`+dvt_wreal`	SystemVerilog Only	Enables wreal extended syntax for Verilog/SystemVerilog files.
`-extinclude`	vcs.vlogan Compatibility Mode-Specific	The included files are parsed using the syntax as specified by directives, that is using by ext syntax (if explicit) or the syntax for unmapped extensions. It overrides the default behavior.
`+incdir+<path>` `-incdir <path>`	SystemVerilog Only	Indicate search directories for files included with `include preprocessing directive.
`+libext+<ext1>+<ext2>+<extN>` `-libext <ext1>,<ext2>,<extN>`	SystemVerilog Only -libext is xcelium.xrun and ius.irun modes specific	Specify accepted extensions for files in the library directories. Extensions must include the ‘.’ dot character. In xcelium.xrun and ius.irun compatibility mode, either plus ‘+’ or comma ‘,’ may be used as extension list separator for either directive. Note There are no default extensions, .v and .sv don’t have a special status.
`-liblist <lib1>[+<lib2>+...]`	vcs.vlogan Compatibility Mode-Specific SystemVerilog Only	Specify the library search order for Verilog packages.
`-libmap <path>`		Specify the Verilog library map file.
`+librescan` `-librescan`		When DVT finds an unresolved module reference in a library file or directory, it will scan for the unresolved reference starting from the first specified library; by default (librescan not specified) it starts scanning from the library that introduced the unresolved reference and continues using the specified libraries order.
`-lps_1801 <upf_file>` `-lps_cpf <upf_file>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific SystemVerilog and VHDL Only	Specify a UPF or CPF power format file for compilation.
`-makelib <lib_name>` `-makelib /path/to/ <lib_name>` `-makelib /some/path:<lib_name>` `... -endlib`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific questa.qrun Compatibility Mode-Specific	Compiles files specified inside a - makelib … - endlib section into the <lib_name> library. Files in makelib sections are compiled before files in the enclosing invocation. Directives in the makelib section only apply to the makelib section files. Directives in the enclosing invocation apply to all files in the invocation. The - work directive is ignored within a makelib section.
`+nctop+<config_name>` `+xmtop+<config_name>`	GLOBAL SystemVerilog Only	Specify a design top module or configuration name. You can specify multiple tops by using this directive multiple times.
`-objext <ext>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `-o_ext +<ext>[,<ext>]`
`-ovm` `-uvm`		In dvt and vcs.vlogan Compatibility Modes it is equivalent with +incdir+/path/to/xvm/src /path/to/xvm/src/xvm_pkg.sv where /path/to/xvm is $XVM_HOME or $DVT_XVM_HOME if $XVM_HOME is not defined, where XVM is a shorthand for OVM / UVM. In the ius.irun and questa.vlo Compatibility Modes /path/to/xvm is automatically located within the IUS resp. Questa installation dirs. See ius.irun Compatibility Mode, questa.vlog Compatibility Mode and questa.qrun Compatibility Mode for more details.
`-ovmhome` `-uvmhome`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific questa.qrun Compatibility Mode-Specific	Load the OVM / UVM library from the specified <path>. See xcelium.xrun Compatibility Mode, ius.irun Compatibility Mode or questa.qrun Compatibility Mode for more details.
`-ml_uvm`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Load the UVM_ML library from the IUS installation location.
`-uvmexthome <path>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific questa.qrun Compatibility Mode-Specific	Load the UVM extension files from the specified <path>. See xcelium.xrun Compatibility Mode, ius.irun Compatibility Mode or questa.qrun Compatibility Mode for more details.
`-pa_upf <upf_file>`	questa.vlog, questa.vcom and questa.qrun Compatibility Mode-Specific SystemVerilog and VHDL Only	Specify a UPF power format file for compilation.
`-pkgsearch <lib>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific SystemVerilog Only	Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
`-reflib <lib>`	questa.qrun Compatibility Mode-Specific SystemVerilog Only	Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
`-realport`	vcs.vlogan Compatibility Mode-Specific SystemVerilog Only	Enables wreal extended syntax for Verilog/SystemVerilog files.
`-setenv <NAME>[=VALUE]`		Equivalent to `+dvt_setenv+<NAME>[=VALUE]`
`-sndefine <arg>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `+define+<arg>`
`-snpath <path>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `+dvt_setenv+SPECMAN_PATH=$SPECMAN_PATH:<path>`
`-sv`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a Verilog syntax flavor will be parsed with SystemVerilog 2012 instead. Has precedence over `-v1995`.
`-sv_lib <file_path>`	GLOBAL	Specify a shared object C/C++ library. The <file_path> should be specified without the .so extension. Provided that the library contains debug info, DVT will Auto-Link the C/C++ source files from which the library was compiled. The .so extension is automatically appended to the specified path. Note If <file_path>.so is not found, the tool will try to locate and load <file_path> instead.
`-sv_liblist <file_path>`	GLOBAL	Specify a shared object bootstrap file. The file contains a list of shared object C/C++ library paths, one per line. For each library in the bootstrap file, provided that the library contains debug info, DVT will Auto-Link the C/C++ source files from which the library was compiled. The .so extension is automatically appended to the paths specified in the bootstrap file.
`-sv root <directory_path>`	GLOBAL	The root directory path is prepended to any relative path that will be specified following this directive, using either `-sv_lib` or `-sv_liblist` or inside the shared object bootstrap file.
`-sverilog`	vcs.vlogan Compatibility Mode-Specific	Sets the syntax for unmapped extensions to SystemVerilog. This directive has precedence over `+v2k`.
`-svams_2019`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	All Verilog/SystemVerilog files will be parsed with SystemVerilog AMS. Has precedence over other syntax specifications.
`-<syntax>_ext [+]<ext>[,<ext>]`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Files with <ext> extension will be parsed using the specified <syntax>. If the optional + is specified, the mapping will be added to the default File Extension to Language Syntax Mapping. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default File Extension to Language Syntax Mapping will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - vlog_ext .svh,.svp. The dot (.) for specifying <ext> is mandatory. The following directives are supported: `-a_ext`, `-amsvhdl_ext`, `-amsvlog_ext`, `-as_ext`, `-c_ext`, `-cpp_ext`, `-dynlib_ext`, `-e_ext`, `-o_ext`, `-spice_ext`, `-sysv_ext`, `-vhcfg_ext`, `-vhdl_ext`. See xcelium.xrun Compatibility Mode or ius.irun Compatibility Mode for more details regarding <syntax>.
`+systemverilogext+<ext>`	vcs.vlogan Compatibility Mode-Specific	All files with <ext> extension are parsed using the SystemVerilog syntax.
`-top <config_name1>[+<config_name2>+...]`	GLOBAL SystemVerilog Only	Specify a design top module or configuration name. You can specify multiple tops either by using the directive multiple times or by specifying multiple top names separated by the ‘+’ character or a combination thereof.
`+UVM_TESTNAME`	GLOBAL	The name of the UVM test which will be automatically created under uvm_root.
`-upf <upf_file>`	vcs.vlogan and vcs.vhdlan Compatibility Mode-Specific SystemVerilog and VHDL Only	Specify a UPF power format file for compilation.
`-v <path>`		Specify a Verilog library file.
`-v1995` `-v95`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with Verilog 2001 will be parsed instead with a reduced keywordset variant of Verilog 2001. The reduced keywordset does not contain the keywords automatic, localparam, generate, endgenerate, and genvar.
`-v200x`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 2008 instead. Has precedence over `-v93`.
`-v93`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	All files that would be parsed according to the File Extension to Language Syntax Mapping or Language Syntax for Unmapped Extensions with a VHDL syntax flavor (but not VHDL AMS) will be parsed with VHDL 93 instead.
`+v2k`	vcs.vlogan Compatibility Mode-Specific	Sets the syntax for unmapped extensions to Verilog 2001.
`+verilog1995ext+<ext>`	vcs.vlogan Compatibility Mode-Specific	All files with <ext> extension are parsed using the Verilog 1995 syntax.
`+verilog2001ext+<ext>`	vcs.vlogan Compatibility Mode-Specific	All files with <ext> extension are parsed using the Verilog 2001 syntax.
`-vhdl87`	vcs.vhdlan Compatibility Mode-Specific	Sets the syntax for unmapped extensions to VHDL 1076-1987.
`-vhdlext <ext>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `-vhdl_ext +<ext>[,<ext>]`
`-vlogext <ext>`	xcelium.xrun Compatibility Mode-Specific ius.irun Compatibility Mode-Specific	Equivalent to `-vlog_ext +<ext>[,<ext>]`
`-w <lib>` `-work <lib>`	vcs.vhdlan Compatibility Mode-Specific	Compile intro library <lib>.
`-work <lib>`		Compile into library <lib>.
`-wreal <res_func>`	vcs.vlogan Compatibility Mode-Specific SystemVerilog Only	Enables wreal extended syntax for Verilog/SystemVerilog files.
`-y <path>`		Specify a Verilog library directory.