Macros

Defined Control Defines

Name	Description
SIMULATION_VALUE_REDUCED	synopsys translate_off Reduced 512 time slot (for simulation)

Undefined Control Defines

Name	Description
EMAC_10_100_MBPS

Defines

Name	Value	Description
AE_BIT	2
ARB_IDLE	3'b000	ARBITER states
ARB_RX	3'b010
ARB_RX_DS	3'b100
ARB_S0	3'b001
ARB_TX	3'b011
ARB_TX_DS	3'b101
ARB_TX_UPD	3'b110
BF_BIT	9
BK_DONE	1'b1	Backoff DONE state (wait slot_cnt tobe equal bk_ended value)
BK_IDLE	1'b0	Backoff IDLE state (wait for pi_bk_start command)
CC_BIT	5:2
CDID_DEVICE_TYPE	16'h3030
CE_BIT	1
CFID_MAC_ID	16'h1010
CFID_MANUFACTURER_ID	16'h2020
DATA	3'h7
DATA_DROP	3'h2
DATA_READ	3'h1
DEVADDR	3'h4
DE_BIT	0
EC_BIT	6
EF_BIT	4
ERROR_LENGTH	8'h04
FC_DEST_ADDR	48'h0180C2000001	Control frame destination address
FC_IDLE	2'd0	FSM states encoding (flow control frame FSM)
FC_OP_TYPE	2'd1
FC_READ	3'h4
FC_TIME_VAL	2'd2
FC_WAIT_64	2'd3
FL_BIT	22:8	Statistic word bits
HASH	3'd2
HOST_NOP	2'b00
HOST_READ	2'b10	HOST bus interface operations
HOST_WRITE	2'b01
IDLE	3'd0	FSM States And Control Data Define *
LC_BIT	7
LE_BIT	3
LP_BIT	7
MATCH_1	3'd3
MATCH_2	3'd4
MF_BIT	6
MULTICAST_BIT	40	Global multicast bit (see 802.3-2002_part2.pdf, 22.2.3 Frame structure)
OF_BIT	0
OPCODE	3'h3
PREAMBLE	3'h1
REGADDR	3'h5
REGS_HWRITE	3'b100
REGS_IDLE	3'b000
REGS_READ	3'b010
REGS_WRITE	3'b001
RX_CRC_CHECK	32'hC704DD7B	CRC check value
RX_DA	4'h3
RX_DATA_0	4'h6
RX_DATA_1	4'h7
RX_DS_IDLE	3'b000	RX ds aquire state values
RX_DS_MAIN	3'b001
RX_DS_READ	3'b010
RX_DS_SUSPEND	3'b011
RX_DS_WAIT	3'b100
RX_ERROR_DATA	8'h1f
RX_EXTEND	4'h8
RX_EXTEND_DATA	8'h0f
RX_FCOPTYPE_CHECK_0	8'h88	FC frame opcode
RX_FCOPTYPE_CHECK_1	8'h08
RX_FCOPTYPE_CHECK_2	8'h00
RX_FCOPTYPE_CHECK_3	8'h01
RX_IDLE	4'h0	FSM states encoding (receive frame)
RX_PREAMBLE	4'h1
RX_PREAMBLE_DATA	4'h5	GMII Data encoding
RX_READ_DS	3'b001
RX_SA	4'h4
RX_SFD	4'h2
RX_SFD_DATA	4'hd
RX_STAT	3'b101
RX_TYPE	4'h5
RX_WAIT	4'h9
RX_WRITE	3'b011
RX_WRITE_DS	3'b110
RX_WRITE_PAUSE	3'b010
SPLIT_IDLE	3'h0	FSM states encoding
SPLIT_WAIT	3'h3
START	3'h2
TJ_BIT	8
TL_BIT	5
TP	1	Delay assertion output signals
TURNAR	3'h6
TX_BACKOFF	4'h8
TX_BEGIN	4'd0	Defer State Coding Transmit IFG initialize after reset (only)
TX_CARRIER	4'd7	Carrier monitor (after remote transmit)
TX_CRC	4'h6
TX_CRS_ERR	4'hd
TX_CRS_JAM	4'hc
TX_DATA	4'h4
TX_DEFER	4'h1
TX_DS_IDLE	3'b000	TX ds aquire state values
TX_DS_MAIN	3'b001
TX_DS_READ	3'b010
TX_DS_SUSPEND	3'b011
TX_DS_UPD_IDLE	2'b00
TX_DS_UPD_WRITE	2'b01
TX_DS_WAIT	3'b100
TX_ERROR	4'd3	Collision during carrier extend phase
TX_ERROR_DATA	8'h1f
TX_EXTEND	4'h9
TX_EXTEND_DATA	4'hf
TX_IDLE	4'd1	Transmit enable
TX_IDLE_DATA	8'h00
TX_IFG1	4'd5	IFG1 (ignore the carrier sense assertion)
TX_IFG2	4'd6	IFG2 (ignore the carrier sense assertion)
TX_JAM	4'd2	Collision during data phase
TX_JAM_DATA	4'hf
TX_JAM_NIBBLE	4'hf
TX_LATENCY	4'd8	MAC latency 2 cycles
TX_LW_BUFF	4'b1000
TX_LW_BURST	4'b1001
TX_LW_DS	4'b0111
TX_LW_FRM	4'b0110
TX_MAC_JABBER_WORDS_LIMIT	16'h1001
TX_PAD	4'h5
TX_PAD_DATA	4'h0
TX_PREAMBLE	4'h2
TX_PREAMBLE_DATA	4'h5
TX_READ	4'b0011
TX_READ_DS	4'b0001
TX_READ_PAUSE	4'b0010
TX_SFD	4'h3
TX_SFD_DATA	4'hd
TX_STOP	4'hb
TX_UPD_FIFO_RANGE	3	range of the tx descriptor update fifo =log2(TX_UPD_FIFO_SIZE)
TX_UPD_FIFO_SIZE	8	size of the tx descriptor update fifo
TX_UPD_WAIT	4'b0101
TX_WAIT	4'd4	Wait carrier to be deasserted after own transmit
TX_WRITE_DS	4'b0100
UF_BIT	1
WAIT	3'd1
WRITE_1	3'd1	Write table (write odd word)
WRITE_2	3'd2	and exact address match 16-bits (when last Hash + 1 Exact Address Match) Write table exact address match 16-bits (1 Exact Address Match)
WRITE_3	3'd3	Write table exact address match 16-bits (1 Exact Address Match)
WRITE_4	3'd4	Write table exact address match 16-bits (1 Exact Address Match)
WR_DATA	3'd1
WR_EXTEND	3'd4
WR_IDLE	3'd0	FSM states encoding (memory write FSM)
WR_OVERRUN	3'd2
WR_STAT	3'd3

×