Features

  • Compatible with the IEEE 802.3–2002 standard

  • Configurable 10/100/1000 Mbps speed

  • IEEE Std 802.3-2002 compliant Media Independent Interface for connection to external 10/100 Mbps PHY transceivers

  • IEEE Std 802.3-2002 compliant Gigabit Media Independent Interface for connection to external 1000 Mbps PHY transceivers

  • Supports 10BASE-T and 100BASE-TX/FX IEEE Std 802.3-2002 compliant MII PHY’s at full or half duplex operating modes

  • Supports Gigabit Ethernet and 1000BASE-T IEEE Std 802.3-2002 compliant GMII PHY’s at full or half duplex operating modes

  • Supports MDIO management control writes and reads with the PHY’s

  • Configurable Full/Half Duplex for any speed

  • Supports burst operation and carrier extend when 1000 Mbps operating mode is selected

  • CSMA/CD compliant operation at 10 Mbps, 100 Mbps, 1000 Mbps in half duplex mode

  • Pause frame capability IEEE 802.3x compliant

  • Backpressure half duplex flow control algorithm

  • Supports Jumbo frame transfer, up to 16KB, both receive and transmit

  • Configurable address filtering modes: 16 perfect addresses, 512 hash-filtered multicast addresses and one perfect address, inverse perfect filtering

  • Supports unicast, multicast, and broadcast

  • Supports promiscuous address receive mode

  • Provides auto pad and Frame Check Sequence field insertion for transmit operation

  • Provides auto Frame Check Sequence field checking and removal for receive operation

  • Programmable interframe gap

  • Internal FIFO’s for TX/RX data flows (configurable size); implemented in Dual port RAM

  • Internal loop-back capability

  • 32-bit Host interface supporting DMA descriptor base system (Tulip Driver) with one general interrupt line

  • Configurable DMA transfer burst length

  • Big/little endian for DMA data transfers

  • Descriptor/buffer architecture, supporting ring/chain data structures

  • Automatic descriptor polling

  • Contains Control and Status Registers Block (CSR)

  • Provides global and per frame statistics for both transmit and receive

  • Supports a wide range of Host clock frequencies

  • Low power capability for all internal blocks independently (gating clock mechanism used when no activity)