Class uvm_reg_mem_shared_access_seq

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_transaction

      • uvm_pkg :: uvm_sequence_item

        • uvm_pkg :: uvm_sequence_base

          • uvm_pkg :: uvm_sequence

            • uvm_pkg :: uvm_reg_sequence

              • uvm_pkg :: uvm_reg_mem_shared_access_seq

Collaboration Diagram of uvm_reg_mem_shared_access_seq

Verify the accessibility of all shared registers and memories in a block by executing the uvm_reg_shared_access_seq and uvm_mem_shared_access_seq sequence respectively on every register and memory within it.

If bit-type resource named "NO_REG_TESTS", "NO_MEM_TESTS", "NO_REG_SHARED_ACCESS_TEST" or "NO_MEM_SHARED_ACCESS_TEST" in the "REG::" namespace matches the full name of the block, the block is not tested.

uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
                           "NO_REG_TESTS", 1, this);

Constructors

function new ( string name )

Tasks

virtual function body ( )

Executes the Shared Register and Memory sequence

virtual function reset_blk ( uvm_reg_block blk )

Reset the DUT that corresponds to the specified block abstraction class.

Currently empty. Will rollback the environment's phase to the reset phase once the new phasing is available.

In the meantime, the DUT should be reset before executing this test sequence or this method should be implemented in an extension to reset the DUT.

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