[source]

Class uvm_reg_predictor

uvm_pkg::uvm_reg_predictor <BUSTYPE> + adapter : uvm_reg_adapter + bus_in : uvm_analysis_imp #(BUSTYPE, uvm_reg_predictor) + map : uvm_reg_map + reg_ap : uvm_analysis_port #(uvm_reg_item) + type_name : string + check_phase(): void + get_object_type(): uvm_object_wrapper + get_type(): type_id + get_type_name(): string + pre_predict(): void + write(): void uvm_pkg::uvm_analysis_imp <T, IMP> uvm_pkg::uvm_analysis_port <T> uvm_pkg::uvm_reg_map uvm_pkg::uvm_reg_adapter bus_in reg_ap map adapter

Collaboration Diagram of uvm_reg_predictor

Updates the register model mirror based on observed bus transactions

This class converts observed bus transactions of type BUSTYPE to generic registers transactions, determines the register being accessed based on the bus address, then updates the register's mirror value with the observed bus data, subject to the register's access mode. See uvm_reg::predict for details.

Memories can be large, so their accesses are not predicted.

Parameters

Name

Default value

Description

BUSTYPE

int

Variables

Name

Type

Description

bus_in

uvm_analysis_imp#(int, uvm_reg_predictor#(int))

Observed bus transactions of type BUSTYPE are received from this port and processed.

For each incoming transaction, the predictor will attempt to get the register or memory handle corresponding to the observed bus address.

If there is a match, the predictor calls the register or memory's predict method, passing in the observed bus data. The register or memory mirror will be updated with this data, subject to its configured access behavior--RW, RO, WO, etc. The predictor will also convert the bus transaction to a generic uvm_reg_item and send it out the reg_ap analysis port.

If the register is wider than the bus, the predictor will collect the multiple bus transactions needed to determine the value being read or written.

reg_ap

uvm_analysis_port#(uvm_reg_item)

Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in .

map

uvm_reg_map

The map used to convert a bus address to the corresponding register or memory handle. Must be configured before the run phase.

adapter

uvm_reg_adapter

The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum. The uvm_reg_adapter must be configured before the run phase.

type_name

string

This method is documented in uvm_object

Constructors

function new ( string name, uvm_component parent ) [source]

Create a new instance of this type, giving it the optional name and parent .

Functions

virtual function string get_type_name ( ) [source]
virtual function void pre_predict ( uvm_reg_item rw ) [source]

Override this method to change the value or re-direct the target register

virtual function void write ( int tr ) [source]

Function- write

not a user-level method. Do not call directly. See documentation for the bus_in member.

virtual function void check_phase ( uvm_phase phase ) [source]

Checks that no pending register transactions are still queued.