Class uvm_reg_predictor
Name |
Default value |
Description |
---|---|---|
BUSTYPE |
int |
Name |
Type |
Description |
---|---|---|
bus_in |
Observed bus transactions of type BUSTYPE are received from this port and processed. For each incoming transaction, the predictor will attempt to get the register or memory handle corresponding to the observed bus address. If there is a match, the predictor calls the register or memory's predict method, passing in the observed bus data. The register or memory mirror will be updated with this data, subject to its configured access behavior--RW, RO, WO, etc. The predictor will also convert the bus transaction to a generic uvm_reg_item and send it out the reg_ap analysis port. If the register is wider than the bus, the predictor will collect the multiple bus transactions needed to determine the value being read or written. |
|
reg_ap |
Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in . |
|
map |
The map used to convert a bus address to the corresponding register or memory handle. Must be configured before the run phase. |
|
adapter |
The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum. The uvm_reg_adapter must be configured before the run phase. |
|
type_name |
string |
This method is documented in uvm_object |
Constructors
- function new ( string name, uvm_component parent ) [source]
Create a new instance of this type, giving it the optional name and parent .
Functions
- virtual function void pre_predict ( uvm_reg_item rw ) [source]
Override this method to change the value or re-direct the target register
Updates the register model mirror based on observed bus transactions
This class converts observed bus transactions of type BUSTYPE to generic registers transactions, determines the register being accessed based on the bus address, then updates the register's mirror value with the observed bus data, subject to the register's access mode. See uvm_reg::predict for details.
Memories can be large, so their accesses are not predicted.