Class uvm_port_base

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_port_base

Inheritance Diagram of uvm_port_base

Collaboration Diagram of uvm_port_base

CLASS

uvm_port_base #(IF)

Transaction-level communication between components is handled via its ports, exports, and imps, all of which derive from this class.

The uvm_port_base extends IF, which is the type of the interface implemented by derived port, export, or implementation. IF is also a type parameter to uvm_port_base.

IF

The interface type implemented by the subtype to this base port

The UVM provides a complete set of ports, exports, and imps for the OSCI- standard TLM interfaces. They can be found in the ../src/tlm/ directory. For the TLM interfaces, the IF parameter is always <uvm_tlm_if_base #(T1,T2)>.

Just before uvm_component::end_of_elaboration_phase, an internal uvm_component::resolve_bindings process occurs, after which each port and export holds a list of all imps connected to it via hierarchical connections to other ports and exports. In effect, we are collapsing the port's fanout, which can span several levels up and down the component hierarchy, into a single array held local to the port. Once the list is determined, the port's min and max connection settings can be checked and enforced.

uvm_port_base possesses the properties of components in that they have a hierarchical instance path and parent. Because SystemVerilog does not support multiple inheritance, uvm_port_base cannot extend both the interface it implements and uvm_component. Thus, uvm_port_base contains a local instance of uvm_component, to which it delegates such commands as get_name, get_full_name, and get_parent.

Parameters

Name	Default value	Description
IF	uvm_void

Typedefs

Name	Actual Type	Description
this_type	uvm_port_base#(IF)

Constructors

function new ( string name, uvm_component parent, uvm_port_type_e port_type, int min_size, int max_size )

The first two arguments are the normal uvm_component constructor arguments.

The port_type can be one of <UVM_PORT>, <UVM_EXPORT>, or <UVM_IMPLEMENTATION>.

The min_size and max_size specify the minimum and maximum number of implementation (imp) ports that must be connected to this port base by the end of elaboration. Setting max_size to UVM_UNBOUNDED_CONNECTIONS sets no maximum, i.e., an unlimited number of connections are allowed.

By default, the parent/child relationship of any port being connected to this port is not checked. This can be overridden by configuring the port's check_connection_relationships bit via uvm_config_int::set() . See connect for more information.

Functions

function string get_name ( )

Returns the leaf name of this port.

virtual function string get_full_name ( )

Returns the full hierarchical name of this port.

virtual function uvm_component get_parent ( )

Returns the handle to this port's parent, or null if it has no parent.

virtual function uvm_port_component_base get_comp ( )

Returns a handle to the internal proxy component representing this port.

Ports are considered components. However, they do not inherit uvm_component. Instead, they contain an instance of <uvm_port_component #(PORT)> that serves as a proxy to this port.

virtual function string get_type_name ( )

Returns the type name to this port. Derived port classes must implement this method to return the concrete type. Otherwise, only a generic "uvm_port", "uvm_export" or "uvm_implementation" is returned.

function int max_size ( )

Function

min_size

Returns the minimum number of implementation ports that must be connected to this port by the end_of_elaboration phase.

function int min_size ( )

Function

max_size

Returns the maximum number of implementation ports that must be connected to this port by the end_of_elaboration phase.

function bit is_unbounded ( )

Returns 1 if this port has no maximum on the number of implementation ports this port can connect to. A port is unbounded when the max_size argument in the constructor is specified as UVM_UNBOUNDED_CONNECTIONS .

function bit is_port ( )

function bit is_export ( )

function bit is_imp ( )

Returns 1 if this port is of the type given by the method name, 0 otherwise.

function int size ( )

Gets the number of implementation ports connected to this port. The value is not valid before the end_of_elaboration phase, as port connections have not yet been resolved.

function void set_if ( int index )

function void set_default_index ( int index )

Sets the default implementation port to use when calling an interface method. This method should only be called on UVM_EXPORT types. The value must not be set before the end_of_elaboration phase, when port connections have not yet been resolved.

virtual function void connect ( this_type provider )

Connects this port to the given provider port. The ports must be compatible in the following ways

• Their type parameters must match

• The provider 's interface type (blocking, non-blocking, analysis, etc.) must be compatible. Each port has an interface mask that encodes the interface(s) it supports. If the bitwise AND of these masks is equal to the this port's mask, the requirement is met and the ports are compatible. For example, a uvm_blocking_put_port #(T) is compatible with a uvm_put_export #(T) and uvm_blocking_put_imp #(T) because the export and imp provide the interface required by the uvm_blocking_put_port.

• Ports of type <UVM_EXPORT> can only connect to other exports or imps.

• Ports of type <UVM_IMPLEMENTATION> cannot be connected, as they are bound to the component that implements the interface at time of construction.

In addition to type-compatibility checks, the relationship between this port and the provider port will also be checked if the port's check_connection_relationships configuration has been set. (See new for more information.)

Relationships, when enabled, are checked are as follows

• If this port is a UVM_PORT type, the provider can be a parent port,

  or a sibling export or implementation port.

• If this port is a <UVM_EXPORT> type, the provider can be a child export or implementation port.

If any relationship check is violated, a warning is issued.

Note- the uvm_component::connect_phase method is related to but not the same as this method. The component's connect method is a phase callback where port's connect method calls are made.

function void debug_connected_to ( int level, int max_level )

The debug_connected_to method outputs a visual text display of the port/export/imp network to which this port connects (i.e., the port's fanout).

This method must not be called before the end_of_elaboration phase, as port connections are not resolved until then.

function void debug_provided_to ( int level, int max_level )

The debug_provided_to method outputs a visual display of the port/export network that ultimately connect to this port (i.e., the port's fanin).

This method must not be called before the end_of_elaboration phase, as port connections are not resolved until then.

function void get_connected_to ( uvm_port_list list )

get_connected_to

function void get_provided_to ( uvm_port_list list )

get_provided_to

virtual function void resolve_bindings ( )

This callback is called just before entering the end_of_elaboration phase. It recurses through each port's fanout to determine all the imp destinations. It then checks against the required min and max connections. After resolution, size returns a valid value and get_if can be used to access a particular imp.

This method is automatically called just before the start of the end_of_elaboration phase. Users should not need to call it directly.

function uvm_port_base get_if ( int index )

Returns the implementation (imp) port at the given index from the array of imps this port is connected to. Use size to get the valid range for index. This method can only be called at the end_of_elaboration phase or after, as port connections are not resolved before then.

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