Class uvm_reg_sequence
Name |
Default value |
Description |
---|---|---|
BASE |
uvm_sequence |
Name |
Type |
Description |
---|---|---|
model |
Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence. |
|
adapter |
Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence. |
|
reg_seqr |
Layered upstream "register" sequencer. Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer. |
|
parent_select |
||
upstream_parent |
Constructors
Enums
Functions
- virtual function void put_response ( uvm_sequence_item response_item ) [source]
Function- put_response
not user visible. Needed to populate this sequence's response queue with any bus item type.
Tasks
- virtual function body ( ) [source]
Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_reg_item.
User-defined RegModel test sequences must override body() and not call super.body(), else a warning will be issued and the calling process not return.
- virtual function do_reg_item ( uvm_reg_item rw ) [source]
Executes the given register transaction, rw , via the sequencer on which this sequence was started (i.e. m_sequencer). Uses the configured adapter to convert the register transaction into the type expected by this sequencer.
- virtual function write_reg ( uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno ) [source]
Writes the given register rg using uvm_reg::write, supplying 'this' as the parent argument. Thus,
write_reg(model.regA, status, value);
is equivalent to
model.regA.write(status, value, .parent(this));
- virtual function read_reg ( uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno ) [source]
Reads the given register rg using uvm_reg::read, supplying 'this' as the parent argument. Thus,
read_reg(model.regA, status, value);
is equivalent to
model.regA.read(status, value, .parent(this));
- virtual function poke_reg ( uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno ) [source]
Pokes the given register rg using uvm_reg::poke, supplying 'this' as the parent argument. Thus,
poke_reg(model.regA, status, value);
is equivalent to
model.regA.poke(status, value, .parent(this));
- virtual function peek_reg ( uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno ) [source]
Peeks the given register rg using uvm_reg::peek, supplying 'this' as the parent argument. Thus,
peek_reg(model.regA, status, value);
is equivalent to
model.regA.peek(status, value, .parent(this));
- virtual function update_reg ( uvm_reg rg, uvm_status_e status, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno ) [source]
Updates the given register rg using uvm_reg::update, supplying 'this' as the parent argument. Thus,
update_reg(model.regA, status, value);
is equivalent to
model.regA.update(status, value, .parent(this));
- virtual function mirror_reg ( uvm_reg rg, uvm_status_e status, uvm_check_e check, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno ) [source]
Mirrors the given register rg using uvm_reg::mirror, supplying 'this' as the parent argument. Thus,
mirror_reg(model.regA, status, UVM_CHECK);
is equivalent to
model.regA.mirror(status, UVM_CHECK, .parent(this));
- virtual function write_mem ( uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno ) [source]
Writes the given memory mem using uvm_mem::write, supplying 'this' as the parent argument. Thus,
write_mem(model.regA, status, offset, value);
is equivalent to
model.regA.write(status, offset, value, .parent(this));
- virtual function read_mem ( uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path, uvm_reg_map map, int prior, uvm_object extension, string fname, int lineno ) [source]
Reads the given memory mem using uvm_mem::read, supplying 'this' as the parent argument. Thus,
read_mem(model.regA, status, offset, value);
is equivalent to
model.regA.read(status, offset, value, .parent(this));
- virtual function poke_mem ( uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno ) [source]
Pokes the given memory mem using uvm_mem::poke, supplying 'this' as the parent argument. Thus,
poke_mem(model.regA, status, offset, value);
is equivalent to
model.regA.poke(status, offset, value, .parent(this));
- virtual function peek_mem ( uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind, uvm_object extension, string fname, int lineno ) [source]
Peeks the given memory mem using uvm_mem::peek, supplying 'this' as the parent argument. Thus,
peek_mem(model.regA, status, offset, value);
is equivalent to
model.regA.peek(status, offset, value, .parent(this));
This class provides base functionality for both user-defined RegModel test sequences and "register translation sequences".
When used as a base for user-defined RegModel test sequences, this class provides convenience methods for reading and writing registers and memories. Users implement the body() method to interact directly with the RegModel model (held in the model property) or indirectly via the delegation methods in this class.
When used as a translation sequence, objects of this class are executed directly on a bus sequencer which are used in support of a layered sequencer use model, a pre-defined convert-and-execute algorithm is provided.
Register operations do not require extending this class if none of the above services are needed. Register test sequences can be extend from the base <uvm_sequence #(REQ,RSP)> base class or even from outside a sequence.
Note- The convenience API not yet implemented.