DVT IDE for VS Code SystemVerilog User Guide
Rev. 24.1.20, 4 September 2024
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Installation
System Requirements
Install DVT for VS Code from Marketplace
Install DVT for VS Code from VSIX
Install DVT for VS Code Using a Pre-Packed Distribution
Set the License
User Interface
VS Code User Interface
DVT IDE for VS Code User Interface
Editor
Activity Bar
Side Bar
Status Bar
Panel
Predefined Projects
Build Configurations
Project Natures
Non-top files
default.build
Auto-config
Simulator Log-config
Emulating compiler invocations
Multiple .build Files
Compatibility Modes
Default DVT Compatibility Mode
gcc Compatibility Mode
ius.irun Compatibility Mode
ius.perspec Compatibility Mode
questa.vcom Compatibility Mode
questa.vlog Compatibility Mode
questa.qrun Compatibility Mode
vcs.vhdlan Compatibility Mode
vcs.vlogan Compatibility Mode
xcelium.xrun Compatibility Mode
Paths
Strings
Comments
Environment Variables
Including Other Argument Files
Build Persistence
All Build Directives
SystemVerilog OVM or UVM Library Compilation
Xilinx Libraries Compilation
Intel(Altera) Quartus Libraries Compilation
Questa Libraries Compilation
Use of External Programs
Compile Checks
Compile Waivers
Semantic Checks
Synthesis Checks
Performance Checks
Dead Code Checks
Non Standard Checks
Quick Fix Proposals
Content Assist (Autocomplete)
Content Assist for CamelCase and Underscore
Code Templates
Module Automatic Instantiation
Override Functions Using Autocomplete
Implement Extern Functions Using Autocomplete
Generate Setters and Getters Using Autocomplete
Use Assignment Pattern for Struct Type Variable
Hyperlinks
Show Usages
Show Readers or Writers
Show Call Hierarchy
Show Type Hierarchy
Show Constraints
Show Instances
Peek Exploration
Refactoring
Override Functions
Override Annotation
Override Using Command Palette
Override Using Autocomplete
Generate Setters and Getters
Code Factory
Code Formatting
Whitespace
Indentation
Vertical Alignment
Line Wrapping
Disable Format for Code Sections
Preferences Keys
Breadcrumb Navigation Bar
Design Breadcrumb
Verification Breadcrumb
Scope Breadcrumb
Diagrams
UML Diagrams
UML Diagram Actions
UML Diagram Preferences
UML Diagrams Legend
Design Diagrams
Schematic Diagrams
Flow Diagrams
Block Diagrams
Finite-State Machine Diagrams
Design Diagram Actions
Design Diagram Filters
UVM Components Diagrams
Component Diagrams from Verification Hierarchy
Component Diagrams from Simulation
Component Diagram Actions
Component Diagram Preferences
Component Diagram Filters
WaveDrom Timing Diagrams
Bit Field Diagrams
Bit Field Diagrams for UVM registers
Bit Field Diagrams for packed data types
Common Diagram Actions
Common Diagram Toolbar
Syntax Coloring
Tooltips
Comments Formatting
Javadoc
Natural Docs
Workspace Symbols
Views
Compile Order View
Build Config Hierarchy
Compiled Files View
Config DB View
Design Hierarchy View
Diagnostics View
Factory Overrides View
Outline View
Problems View
Registers View
Verification Hierarchy View
Quick Search in Views
CamelCase
Simple Regex
Hierarchical Search
Search for Members
Search Port in Design Hierarchy
Search Port in Verification Hierarchy
Content Filters
Content Filters XML Syntax
Filtering by Element Type
Content Filters Examples
Predefined Content Filters
Macros Support
Inactive Code Highlight
Macro Expansion
Inactive Generates Code Highlight
Database Out of Sync Notification
Export HTML/PDF Documentation
Preview HTML Documentation
External Tools Integration
UVM Support
UVM Runtime Elaboration
Runtime UVM Configuration Queries
UVM Content Filters
UVM Sequence Tree
UVM Templates
UVM Verification Hierarchy
Scripts
dvt_code.sh
dvt_code.sh Syntax
dvt_code.sh Examples
dvt_ls.sh
dvt_ls.sh Syntax
dvt_ls.sh Examples
Custom Scripts
SCM Checkout Hook
Memory Monitor
Application Notes
Flow Integration
Environment Variables
Design Elaboration
Top candidates
Parameter values
Unelaborated Design
Debugging
Performance
Compilation Speed-up
Precompilation Support
Encrypted VIP Support
FPGA Support
Intel(Altera) Quartus
Intel(Altera) Quartus Libraries Compilation
Xilinx ISE/Vivado
Xilinx Libraries Compilation
Preprocessed Files Support
Output and logging
Understanding DVT IDE memory usage
Handy VS Code Documentation Pointers
What is New?
How to Report an Issue?
Legal Notices
Third Party Licenses
Q & A
Can I deactivate DVT support for a workspace even though one of my workspace folders contains a .dvt directory?
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DVT IDE for VS Code SystemVerilog User Guide
Table of Contents
1. Installation
1.1. System Requirements
1.2. Install DVT for VS Code from Marketplace
1.3. Install DVT for VS Code from VSIX
1.4. Install DVT for VS Code Using a Pre-Packed Distribution
1.5. Set the License
2. User Interface
2.1. VS Code User Interface
2.2. DVT IDE for VS Code User Interface
2.2.1. Editor
2.2.2. Activity Bar
2.2.3. Side Bar
2.2.4. Status Bar
2.2.5. Panel
3. Predefined Projects
4. Build Configurations
4.1. Project Natures
4.2. Non-top files
4.3. default.build
4.4. Auto-config
4.5. Simulator Log-config
4.6. Emulating compiler invocations
4.7. Multiple .build Files
4.8. Compatibility Modes
4.8.1. Default DVT Compatibility Mode
4.8.2. gcc Compatibility Mode
4.8.3. ius.irun Compatibility Mode
4.8.4. ius.perspec Compatibility Mode
4.8.5. questa.vcom Compatibility Mode
4.8.6. questa.vlog Compatibility Mode
4.8.7. questa.qrun Compatibility Mode
4.8.8. vcs.vhdlan Compatibility Mode
4.8.9. vcs.vlogan Compatibility Mode
4.8.10. xcelium.xrun Compatibility Mode
4.9. Paths
4.10. Strings
4.11. Comments
4.12. Environment Variables
4.13. Including Other Argument Files
4.14. Build Persistence
4.15. All Build Directives
4.16. SystemVerilog OVM or UVM Library Compilation
4.17. Xilinx Libraries Compilation
4.18. Intel(Altera) Quartus Libraries Compilation
4.19. Questa Libraries Compilation
4.20. Use of External Programs
5. Compile Checks
5.1. Compile Waivers
5.2. Semantic Checks
5.3. Synthesis Checks
5.4. Performance Checks
5.5. Dead Code Checks
5.6. Non Standard Checks
6. Quick Fix Proposals
7. Content Assist (Autocomplete)
7.1. Content Assist for CamelCase and Underscore
7.2. Code Templates
7.3. Module Automatic Instantiation
7.4. Override Functions Using Autocomplete
7.5. Implement Extern Functions Using Autocomplete
7.6. Generate Setters and Getters Using Autocomplete
7.7. Use Assignment Pattern for Struct Type Variable
8. Hyperlinks
9. Show Usages
10. Show Readers or Writers
11. Show Call Hierarchy
12. Show Type Hierarchy
13. Show Constraints
14. Show Instances
15. Peek Exploration
16. Refactoring
17. Override Functions
17.1. Override Annotation
17.2. Override Using Command Palette
17.3. Override Using Autocomplete
18. Generate Setters and Getters
19. Code Factory
20. Code Formatting
20.1. Whitespace
20.2. Indentation
20.3. Vertical Alignment
20.4. Line Wrapping
20.5. Disable Format for Code Sections
20.6. Preferences Keys
21. Breadcrumb Navigation Bar
21.1. Design Breadcrumb
21.2. Verification Breadcrumb
21.3. Scope Breadcrumb
22. Diagrams
22.1. UML Diagrams
22.1.1. UML Diagram Actions
22.1.2. UML Diagram Preferences
22.1.3. UML Diagrams Legend
22.2. Design Diagrams
22.2.1. Schematic Diagrams
22.2.2. Flow Diagrams
22.2.3. Block Diagrams
22.2.4. Finite-State Machine Diagrams
22.2.5. Design Diagram Actions
22.2.6. Design Diagram Filters
22.3. UVM Components Diagrams
22.3.1. Component Diagrams from Verification Hierarchy
22.3.2. Component Diagrams from Simulation
22.3.3. Component Diagram Actions
22.3.4. Component Diagram Preferences
22.3.5. Component Diagram Filters
22.4. WaveDrom Timing Diagrams
22.5. Bit Field Diagrams
22.5.1. Bit Field Diagrams for UVM registers
22.5.2. Bit Field Diagrams for packed data types
22.6. Common Diagram Actions
22.7. Common Diagram Toolbar
23. Syntax Coloring
24. Tooltips
24.1. Comments Formatting
24.1.1. Javadoc
24.1.2. Natural Docs
25. Workspace Symbols
26. Views
26.1. Compile Order View
26.1.1. Build Config Hierarchy
26.2. Compiled Files View
26.3. Config DB View
26.4. Design Hierarchy View
26.5. Diagnostics View
26.6. Factory Overrides View
26.7. Outline View
26.8. Problems View
26.9. Registers View
26.10. Verification Hierarchy View
27. Quick Search in Views
27.1. CamelCase
27.2. Simple Regex
27.3. Hierarchical Search
27.4. Search for Members
27.5. Search Port in Design Hierarchy
27.6. Search Port in Verification Hierarchy
28. Content Filters
28.1. Content Filters XML Syntax
28.2. Filtering by Element Type
28.3. Content Filters Examples
28.4. Predefined Content Filters
29. Macros Support
29.1. Inactive Code Highlight
29.2. Macro Expansion
30. Inactive Generates Code Highlight
31. Database Out of Sync Notification
32. Export HTML/PDF Documentation
32.1. Preview HTML Documentation
33. External Tools Integration
34. UVM Support
34.1. UVM Runtime Elaboration
34.2. Runtime UVM Configuration Queries
34.3. UVM Content Filters
34.4. UVM Sequence Tree
34.5. UVM Templates
34.6. UVM Verification Hierarchy
35. Scripts
35.1. dvt_code.sh
35.1.1. dvt_code.sh Syntax
35.1.2. dvt_code.sh Examples
35.2. dvt_ls.sh
35.2.1. dvt_ls.sh Syntax
35.2.2. dvt_ls.sh Examples
36. Custom Scripts
37. SCM Checkout Hook
38. Memory Monitor
39. Application Notes
39.1. Flow Integration
39.2. Environment Variables
39.3. Design Elaboration
39.3.1. Top candidates
39.3.2. Parameter values
39.3.3. Unelaborated Design
39.3.4. Debugging
39.3.5. Performance
39.4. Compilation Speed-up
39.5. Precompilation Support
39.6. Encrypted VIP Support
39.7. FPGA Support
39.7.1. Intel(Altera) Quartus
39.7.2. Xilinx ISE/Vivado
39.8. Preprocessed Files Support
39.9. Output and logging
39.10. Understanding DVT IDE memory usage
40. Handy VS Code Documentation Pointers
41. What is New?
42. How to Report an Issue?
43. Legal Notices
44. Third Party Licenses
45. Q & A
45.1. Can I deactivate DVT support for a workspace even though one of my workspace folders contains a .dvt directory?