Class uvm_pkg::uvm_reg_access_seq

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_transaction

      • uvm_pkg :: uvm_sequence_item

        • uvm_pkg :: uvm_sequence_base

          • uvm_pkg :: uvm_sequence

            • uvm_pkg :: uvm_reg_sequence

              • uvm_pkg :: uvm_reg_access_seq

Collaboration Diagram of uvm_reg_access_seq

Class

uvm_reg_access_seq

Verify the accessibility of all registers in a block by executing the uvm_reg_single_access_seq sequence on every register within it.

If bit-type resource named "NO_REG_TESTS" or "NO_REG_ACCESS_TEST" in the "REG::" namespace matches the full name of the block, the block is not tested.

 uvm_resource_db#(bit)::set({"REG::",regmodel.blk.get_full_name(),".*"},
                            "NO_REG_TESTS", 1, this);

Constructors

function

new(string name = "uvm_reg_access_seq")

Parameters:

name (string)

Tasks

virtual function

body()

Task

body

Executes the Register Access sequence. Do not call directly. Use seq.start() instead.

virtual function

reset_blk(uvm_reg_block blk)

Task

reset_blk

Reset the DUT that corresponds to the specified block abstraction class.

Currently empty. Will rollback the environment's phase to the reset phase once the new phasing is available.

In the meantime, the DUT should be reset before executing this test sequence or this method should be implemented in an extension to reset the DUT.

Parameters:

blk (uvm_reg_block)

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