[source]

Class uvm_pkg::uvm_reg_sequence

uvm_pkg::uvm_reg_sequence <BASE> + adapter : uvm_reg_adapter + model : uvm_reg_block + parent_select : seq_parent_e + reg_seqr : uvm_sequencer #(uvm_reg_item, uvm_reg_item) + upstream_parent : uvm_sequence_base + __m_uvm_field_automation(): void + body() + create(): uvm_object + do_reg_item() + get_object_type(): uvm_object_wrapper + get_type(): type_id + mirror_reg() + peek_mem() + peek_reg() + poke_mem() + poke_reg() + put_response(): void + read_mem() + read_reg() + update_reg() + write_mem() + write_reg() uvm_pkg::uvm_reg_frontdoor uvm_pkg::uvm_reg_hw_reset_seq uvm_pkg::uvm_reg_single_bit_bash_seq uvm_pkg::uvm_reg_bit_bash_seq uvm_pkg::uvm_mem_single_walk_seq uvm_pkg::uvm_mem_walk_seq uvm_pkg::uvm_mem_single_access_seq uvm_pkg::uvm_mem_access_seq uvm_pkg::uvm_reg_single_access_seq uvm_pkg::uvm_reg_access_seq uvm_pkg::uvm_reg_mem_access_seq uvm_pkg::uvm_reg_shared_access_seq uvm_pkg::uvm_mem_shared_access_seq uvm_pkg::uvm_reg_mem_shared_access_seq uvm_pkg::uvm_reg_mem_built_in_seq uvm_pkg::uvm_reg_mem_hdl_paths_seq <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence> <BASE : uvm_sequence>

Inheritance Diagram of uvm_reg_sequence

uvm_pkg::uvm_reg_sequence <BASE> + adapter : uvm_reg_adapter + model : uvm_reg_block + parent_select : seq_parent_e + reg_seqr : uvm_sequencer #(uvm_reg_item, uvm_reg_item) + upstream_parent : uvm_sequence_base + __m_uvm_field_automation(): void + body() + create(): uvm_object + do_reg_item() + get_object_type(): uvm_object_wrapper + get_type(): type_id + mirror_reg() + peek_mem() + peek_reg() + poke_mem() + poke_reg() + put_response(): void + read_mem() + read_reg() + update_reg() + write_mem() + write_reg() uvm_pkg::uvm_reg_block uvm_pkg::uvm_reg_adapter uvm_pkg::uvm_sequencer <REQ, RSP> uvm_pkg::uvm_sequence_base model adapter reg_seqr upstream_parent

Collaboration Diagram of uvm_reg_sequence

CLASS

uvm_reg_sequence

This class provides base functionality for both user-defined RegModel test sequences and "register translation sequences".

  • When used as a base for user-defined RegModel test sequences, this class provides convenience methods for reading and writing registers and memories. Users implement the body() method to interact directly with the RegModel model (held in the model property) or indirectly via the delegation methods in this class.

  • When used as a translation sequence, objects of this class are executed directly on a bus sequencer which are used in support of a layered sequencer use model, a pre-defined convert-and-execute algorithm is provided.

Register operations do not require extending this class if none of the above services are needed. Register test sequences can be extend from the base <uvm_sequence #(REQ,RSP)> base class or even from outside a sequence.

Note- The convenience API not yet implemented.

Parameters

Name

Default value

Description

BASE

uvm_sequence

Variables

Name

Type

Description

model

uvm_reg_block

Variable

model

Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

adapter

uvm_reg_adapter

Variable

adapter

Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

reg_seqr

uvm_sequencer#(uvm_reg_item, uvm_reg_item)

Variable

reg_seqr

Layered upstream "register" sequencer.

Specifies the upstream sequencer between abstract register transactions and physical bus transactions. Defined only when this sequence is a translation sequence, and we want to "pull" from an upstream sequencer.

parent_select

seq_parent_e

upstream_parent

uvm_sequence_base

Constructors

new(string name = "uvm_reg_sequence_inst")

Function

new

Create a new instance, giving it the optional name .

Parameters:

name (string)

Enums

seq_parent_e
Enum Items:
  • LOCAL

  • UPSTREAM

Functions

put_response(uvm_sequence_item response_item)

Function- put_response

not user visible. Needed to populate this sequence's response queue with any bus item type.

Parameters:

response_item (uvm_sequence_item)

Tasks

body()

Task

body

Continually gets a register transaction from the configured upstream sequencer, reg_seqr, and executes the corresponding bus transaction via do_reg_item.

User-defined RegModel test sequences must override body() and not call super.body(), else a warning will be issued and the calling process not return.

do_reg_item(uvm_reg_item rw)

Function

do_reg_item

Executes the given register transaction, rw , via the sequencer on which this sequence was started (i.e. m_sequencer). Uses the configured adapter to convert the register transaction into the type expected by this sequencer.

Parameters:

rw (uvm_reg_item)

write_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path = UVM_DEFAULT_PATH, uvm_reg_map map = null, int prior = -1, uvm_object extension = null, string fname = "", int lineno = 0)

Task

write_reg

Writes the given register rg using uvm_reg::write, supplying 'this' as the parent argument. Thus,

 write_reg(model.regA, status, value);

is equivalent to

 model.regA.write(status, value, .parent(this));
Parameters:
read_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, uvm_path_e path = UVM_DEFAULT_PATH, uvm_reg_map map = null, int prior = -1, uvm_object extension = null, string fname = "", int lineno = 0)

Task

read_reg

Reads the given register rg using uvm_reg::read, supplying 'this' as the parent argument. Thus,

 read_reg(model.regA, status, value);

is equivalent to

 model.regA.read(status, value, .parent(this));
Parameters:
poke_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind = "", uvm_object extension = null, string fname = "", int lineno = 0)

Task

poke_reg

Pokes the given register rg using uvm_reg::poke, supplying 'this' as the parent argument. Thus,

 poke_reg(model.regA, status, value);

is equivalent to

 model.regA.poke(status, value, .parent(this));
Parameters:
peek_reg(uvm_reg rg, uvm_status_e status, uvm_reg_data_t value, string kind = "", uvm_object extension = null, string fname = "", int lineno = 0)

Task

peek_reg

Peeks the given register rg using uvm_reg::peek, supplying 'this' as the parent argument. Thus,

 peek_reg(model.regA, status, value);

is equivalent to

 model.regA.peek(status, value, .parent(this));
Parameters:
update_reg(uvm_reg rg, uvm_status_e status, uvm_path_e path = UVM_DEFAULT_PATH, uvm_reg_map map = null, int prior = -1, uvm_object extension = null, string fname = "", int lineno = 0)

Task

update_reg

Updates the given register rg using uvm_reg::update, supplying 'this' as the parent argument. Thus,

 update_reg(model.regA, status, value);

is equivalent to

 model.regA.update(status, value, .parent(this));
Parameters:
mirror_reg(uvm_reg rg, uvm_status_e status, uvm_check_e check = UVM_NO_CHECK, uvm_path_e path = UVM_DEFAULT_PATH, uvm_reg_map map = null, int prior = -1, uvm_object extension = null, string fname = "", int lineno = 0)

Task

mirror_reg

Mirrors the given register rg using uvm_reg::mirror, supplying 'this' as the parent argument. Thus,

 mirror_reg(model.regA, status, UVM_CHECK);

is equivalent to

 model.regA.mirror(status, UVM_CHECK, .parent(this));
Parameters:
write_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path = UVM_DEFAULT_PATH, uvm_reg_map map = null, int prior = -1, uvm_object extension = null, string fname = "", int lineno = 0)

Task

write_mem

Writes the given memory mem using uvm_mem::write, supplying 'this' as the parent argument. Thus,

 write_mem(model.regA, status, offset, value);

is equivalent to

 model.regA.write(status, offset, value, .parent(this));
Parameters:
read_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, uvm_path_e path = UVM_DEFAULT_PATH, uvm_reg_map map = null, int prior = -1, uvm_object extension = null, string fname = "", int lineno = 0)

Task

read_mem

Reads the given memory mem using uvm_mem::read, supplying 'this' as the parent argument. Thus,

 read_mem(model.regA, status, offset, value);

is equivalent to

 model.regA.read(status, offset, value, .parent(this));
Parameters:
poke_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind = "", uvm_object extension = null, string fname = "", int lineno = 0)

Task

poke_mem

Pokes the given memory mem using uvm_mem::poke, supplying 'this' as the parent argument. Thus,

 poke_mem(model.regA, status, offset, value);

is equivalent to

 model.regA.poke(status, offset, value, .parent(this));
Parameters:
peek_mem(uvm_mem mem, uvm_status_e status, uvm_reg_addr_t offset, uvm_reg_data_t value, string kind = "", uvm_object extension = null, string fname = "", int lineno = 0)

Task

peek_mem

Peeks the given memory mem using uvm_mem::peek, supplying 'this' as the parent argument. Thus,

 peek_mem(model.regA, status, offset, value);

is equivalent to

 model.regA.peek(status, offset, value, .parent(this));
Parameters: