Class uvm_pkg::uvm_root

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_report_object

      • uvm_pkg :: uvm_component

        • uvm_pkg :: uvm_root

Collaboration Diagram of uvm_root

Variables

Name	Type	Description
clp	uvm_cmdline_processor
finish_on_completion	bit	Variable finish_on_completion If set, then run_test will call $finish after all phases are executed.
top_levels	uvm_component	Variable top_levels This variable is a list of all of the top level components in UVM. It includes the uvm_test_top component that is created by run_test as well as any other top level components that have been instantiated anywhere in the hierarchy.
enable_print_topology	bit	Variable enable_print_topology If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase.
phase_timeout	time

Functions

static function uvm_root

get()

Function

get()

Static accessor for uvm_root.

The static accessor is provided as a convenience wrapper around retrieving the root via the uvm_coreservice_t::get_root method.

 // Using the uvm_coreservice_t:
 uvm_coreservice_t cs;
 uvm_root r;
 cs = uvm_coreservice_t::get();
 r = cs.get_root();

 // Not using the uvm_coreservice_t:
 uvm_root r;
 r = uvm_root::get();. Get

Return type:

uvm_root

virtual function string

get_type_name()

virtual function void

die()

Function

die

This method is called by the report server if a report reaches the maximum quit count or has a UVM_EXIT action associated with it, e.g., as with fatal errors.

Calls the uvm_component::pre_abort() method on the entire uvm_component hierarchy in a bottom-up fashion. It then calls uvm_report_server::report_summarize and terminates the simulation with $finish .

function void

set_timeout(time timeout, bit overridable = 1)

Function

set_timeout

Specifies the timeout for the simulation. Default is [`UVM_DEFAULT_TIMEOUT](../../../../index-macros.html#macros)

The timeout is simply the maximum absolute simulation time allowed before a FATAL occurs. If the timeout is set to 20ns, then the simulation must end before 20ns, or a FATAL timeout will occur.

This is provided so that the user can prevent the simulation from potentially consuming too many resources (Disk, Memory, CPU, etc) when the testbench is essentially hung. Set_timeout

Parameters:

• timeout (time)

• overridable (bit)

function uvm_component

find(string comp_match)

Function

find. Find

Parameters:

comp_match (string)

Return type:

uvm_component

function void

find_all(string comp_match, uvm_component comps, uvm_component comp = null)

Function

find_all

Returns the component handle (find) or list of components handles (find_all) matching a given string. The string may contain the wildcards, and ?. Strings beginning with '.' are absolute path names. If the optional argument comp is provided, then search begins from that component down (default=all components). Find_all

Parameters:

• comp_match (string)

• comps (uvm_component)

• comp (uvm_component)

function void

print_topology(uvm_printer printer = null)

Function

print_topology

Print the verification environment's component topology. The printer is a uvm_printer object that controls the format of the topology printout; a null printer prints with the default output. Print_topology

Parameters:

printer (uvm_printer)

virtual function void

build_phase(uvm_phase phase)

Build_phase

Parameters:

phase (uvm_phase)

virtual function void

report_header(UVM_FILE file = 0)

Parameters:

file (UVM_FILE)

virtual function void

phase_started(uvm_phase phase)

phase_started

At end of elab phase we need to do tlm binding resolution.

Parameters:

phase (uvm_phase)

function void

stop_request()

backward compat only call global_stop_request() or uvm_test_done.stop_request() instead

virtual function void

end_of_elaboration_phase(uvm_phase phase)

Parameters:

phase (uvm_phase)

Tasks

virtual function

run_test(string test_name = "")

Task

run_test

Phases all components through all registered phases. If the optional test_name argument is provided, or if a command-line plusarg, +UVM_TESTNAME=TEST_NAME, is found, then the specified component is created just prior to phasing. The test may contain new verification components or the entire testbench, in which case the test and testbench can be chosen from the command line without forcing recompilation. If the global (package) variable, finish_on_completion, is set, then $finish is called after phasing completes. Run_test

Parameters:

test_name (string)

virtual function

run_phase(uvm_phase phase)

For error checking. It is required that the run phase start at simulation time 0

TBD this looks wrong

taking advantage of uvm_root not doing anything else? TBD move to phase_started callback?

Parameters:

phase (uvm_phase)

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