[source]

Class uvm_pkg::uvm_reg_predictor

uvm_pkg :: uvm_void
- uvm_pkg :: uvm_object
  
  uvm_pkg :: uvm_report_object
  
  uvm_pkg :: uvm_component
  
  uvm_pkg :: uvm_reg_predictor

Collaboration Diagram of uvm_reg_predictor

CLASS

uvm_reg_predictor

Updates the register model mirror based on observed bus transactions

This class converts observed bus transactions of type BUSTYPE to generic registers transactions, determines the register being accessed based on the bus address, then updates the register's mirror value with the observed bus data, subject to the register's access mode. See uvm_reg::predict for details.

Memories can be large, so their accesses are not predicted.

Parameters
Name	Default value	Description
BUSTYPE	int

Variables
Name	Type	Description
bus_in	uvm_analysis_imp#(int, uvm_reg_predictor#(int))	Variable bus_in Observed bus transactions of type BUSTYPE are received from this port and processed. For each incoming transaction, the predictor will attempt to get the register or memory handle corresponding to the observed bus address. If there is a match, the predictor calls the register or memory's predict method, passing in the observed bus data. The register or memory mirror will be updated with this data, subject to its configured access behavior--RW, RO, WO, etc. The predictor will also convert the bus transaction to a generic uvm_reg_item and send it out the reg_ap analysis port. If the register is wider than the bus, the predictor will collect the multiple bus transactions needed to determine the value being read or written.
reg_ap	uvm_analysis_port#(uvm_reg_item)	Variable reg_ap Analysis output port that publishes uvm_reg_item transactions converted from bus transactions received on bus_in .
map	uvm_reg_map	Variable map The map used to convert a bus address to the corresponding register or memory handle. Must be configured before the run phase.
adapter	uvm_reg_adapter	Variable adapter The adapter used to convey the parameters of a bus operation in terms of a canonical uvm_reg_bus_op datum. The uvm_reg_adapter must be configured before the run phase.
type_name	string	This method is documented in uvm_object

Constructors

new(string name, uvm_component parent)

Function

new

Create a new instance of this type, giving it the optional name and parent .

Parameters:

name (string)
parent (uvm_component)

Functions

get_type_name()

pre_predict(uvm_reg_item rw)

Function

pre_predict

Override this method to change the value or re-direct the target register

Parameters:: rw (uvm_reg_item)

write(int tr)

Function- write

not a user-level method. Do not call directly. See documentation for the bus_in member.

Parameters:: tr (int)

check_phase(uvm_phase phase)

Function

check_phase

Checks that no pending register transactions are still queued.

Parameters:: phase (uvm_phase)