Rajendran Munuswamy

I was looking for subsystems modeling and simulation in the FPGA environment for control-serial-protocols and bus protocols through APB, AHB, AXI, which eventually led me to learn about UVM-test environment learning in an integrated simulation environment.

Heard about AMIQ’s DVT Eclipse IDE through Youtube channels, surely a key tool to be utilized under one umbrella.

The basic features I have utilized are the Quick linter with advanced Semantic checks, Code completion for SV/UVM, bundled with many more customizations. All under one package is a big surprise to engineers. Using the DVT IDE effectively avoids human mistakes (syntax and semantics) and post-simulation-fixing loop, thus saving lot of time. It’s surely a blessing for verification engineers.

I am grateful to our India support team from DelphiumTech, who are dedicated with high spirits, patience and customer centric availability and technical help, all the time.