DVT Eclipse IDE Diagrams - How to Generate Bit Field Diagrams for Packed Data Types

Description

This video shows how you can easily generate bit field diagrams from System Verilog packed data types in the DVT Eclipse IDE.

For more information: https://www.dvteclipse.com/documentation/sv/Bitfield_Diagrams_for_packed_data_types.html

This video was shot using DVT 22.1.36

Transcript

Introduction

Hover a SystemVerilog packed struct or union type inside the editor to visualize the bit field diagram.

Diagram Representation

The members are represented from left to right, from most to least significant.

In order to differentiate member types, check the legend located at the top.

For additional information, such as type or position, click an element from the diagram to highlight it in the table below.

Nested Diagrams for Members

For each member of a packed struct or union type, the bit field diagram of its own type is also presented below the member. Each union member is represented on a separate lane.

Using the Inspect View

The Inspect View controls, and its ability to be maximized, make it more convenient than tooltips for exploration of larger diagrams. Right-click in the Inspect View to save the diagram to a file.