DVT Eclipse IDE Diagrams - How to Generate Diagrams Showing UVM Components and TLM Port Connections

Description

UVM Components Diagrams help you inspect and document the structure of a verification environment. They illustrate the containment of the UVM component instances and the TLM port connections in your verification environment.

This video shows how to generate and explore a UVM Components Diagram.

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Transcript

Generating UVM Component Diagrams

In DVT, you can generate UVM component diagrams for SystemVerilog and eLanguage.

Right-click on an entry in the Verification Hierarchy View and select Show Diagram. The diagram shows the UVM components containment and the TLM port connections.

Navigating the Diagram

• Click and drag to pan.
• Use mouse scroll to zoom in and out.
• Click on the Fit Canvas toolbar button to return to the initial zoom level.
• Use the Inspect Panel toolbar button to quickly get additional information for the selected diagram element.

Navigating between UVM Components Diagram and Source Code

• Right-click on a component or a labeled edge and select Go to Type.
• Click Back in the main toolbar to return to the diagram.
• Right-click on a component and select Go to Create Call for SystemVerilog or Go to Instance for eLanguage.