How to Generate Bit Field Diagrams for Packed Data Types in the DVT IDE for VS Code
Description
This video shows how you can easily generate bit field diagrams from System Verilog packed data types in the DVT IDE for VS Code.
For more information: https://eda.amiq.com/documentation/eclipse/sv/toc/diagrams/bit-field-diagrams.html#bit-field-diagrams-for-packed-data-types
This video was shot using DVT 22.1.36
Transcript
Visualizing Bit Field Diagrams
Hover a SystemVerilog packed struct
or union
type inside the editor to visualize the bit field diagram.
The members are represented from left to right, from most to least significant.
Differentiating Member Types
In order to differentiate member types, check the legend located at the top.
For additional information, such as type or position, check the table below the diagram.
Nested Bit Field Diagrams
For each member of a packed struct
or union
type, the bit field diagram of its own type is also presented below the member.
Each union member is represented on a separate lane.
Diagram Tools and Controls
The diagram's view controls and its ability to be maximized make it more convenient than tooltips for exploration of larger diagrams.
Use the toolbar button to save the diagram to a file.