How to Trace a Signal in the DVT Eclipse IDE - Part I - Tracing From the Design Hierarchy View

Description

This is the first video in a series that explains how to trace signals in the DVT Eclipse IDE for SystemVerilog, Verilog and VHDL.

Follow a signal through instance port connections, concatenations and any type of combinational logic, and stop at the boundary of sequential blocks.

Start tracing from the Design Hierarchy view or directly from the DVT editor. Inspect the trace results in the Trace Connections view.

Transcript

Introduction

DVT allows you to trace drivers and loads for any port or internal signal in your design. Tracing is performed across the current design hierarchy, through port connections and combinational logic, and stops at the boundary of sequential blocks. You can start tracing from the Design Hierarchy View or directly from the DVT Editor. We will focus for now on the first approach.

Open the Design Hierarchy View and click on the Select Top View toolbar button to populate it. Locate the instance port you want to trace. A quick way to do this is by typing . followed by the port name.

Right-click on the port and select one of the available trace operations, for example Trace Drive and Load.

The Trace Connections View opens up, showing you the subset of the design hierarchy influenced by the traced signal.

Note that the drivers and loads are marked accordingly, with red and green target decorations, respectively.

The second video in this series will show you how to further inspect the drive or load path.