Refactoring in the DVT Eclipse IDE - How to Add a New Port or Parameter to a Module

In DVT you can easily add a new port or parameter/generic to a Verilog module or VHDL entity.

Place the editor cursor on the module/entity name, Right-Click and pick Refactor then Add port.

The new port/parameter is added to the declaration, and an empty connection to all of the instances.

In DVT, you can easily add a new port or parameter to a module.

Adding a New Port

Place the editor cursor on the module name, right-click and pick Refactor > Add Port.

In the pop-up dialog, you can change the name, direction, type and width for the new port.

Click Preview to inspect the changes that are about to be performed.

Notice that the new port is added to the module declaration and an empty port connection to all the module instances.

Click OK to perform the refactoring.

Each empty port connection comes along with a FIXME reminder comment, which shows up in the Tasks View.

In a similar way, you can add a new parameter.

Right-click on a module name, select Refactor > Add Parameter.

In the pop-up dialog, add a default value to the new parameter and click OK.