AMIQ EDA Announces Solution for Continuous Integration of SystemVerilog Testbenches

 July 16, 2020, San Jose, California — AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis, today announced a methodology for continuous integration of SystemVerilog testbench code for verification of the most complex semiconductor designs. This novel approach, already adopted by leading semiconductor IP companies such as Arm, involves a combination of established capabilities in Design and Verification Tools (DVT) Eclipse IDE and Verissimo SystemVerilog Testbench Linter, new Verissimo features linking to project management and revision control systems, and best practices developed alongside leading-edge users.

Verissimo provides specialized checks for verification testbenches written in SystemVerilog, enabling projects to employ and enforce coding rules to ensure uniform style, and prevent both functional bugs and performance bugs. In the new methodology, verification teams run Verissimo on a continuous basis to ensure consistent code quality. Some teams run Verissimo automatically every time a change is committed into the project’s revision control system, allowing the change only if no errors are detected. Other teams schedule regular runs, for example every evening, to check all the files changed since the last run.

This process uses the advanced features for comparing reports of rule violations and intelligently filtering the results, as announced earlier this year. Recent enhancements to these capabilities in Verissimo enable continuous integration and leverage the data available in revision control systems. For example, users can generate delta reports over time, and compare the latest changed files against the most recent check-ins, the most recent complete testbench build, a master build, and more. Some revision control systems can report which engineer changed which line and when; Verissimo collects this data and provides even more sophisticated debugging options.

Continuous integration is done automatically, in batch mode. When verification engineers wish to examine and fix errors, they use the advanced graphical features of DVT Eclipse IDE. Verissimo can automatically correct violations for certain classes of coding rules; users review and accept these fixes within the IDE. The result is much less time spent examining reports and debugging reported violations, speeding up verification and reducing time-to-market on critical chip projects.

“Verissimo and DVT Eclipse are being used across Arm in continuous integration flows to help better identify problems in coding and assess project status,” said Tran Nguyen, Director of Design Services, Arm. “The precise feedback helps with coding discipline across large project teams and enables us to deliver optimized designs for a wide range of users.”

“Arm® engineers have suggested additional checks and features in Verissimo based on their expertise and experience, and have helped us develop this new methodology,” said Cristian Amitroaie, CEO of AMIQ EDA. “The result is a SystemVerilog testbench continuous integration flow that benefits all our users and enables them to follow best practices.”


AMIQ EDA provides design and verification engineers with platform-independent software tools that enable them to increase the speed and quality of new code development, simplify debugging and legacy code maintenance, accelerate language and methodology learning, improve testbench reliability, extract automatically accurate documentation, and implement best coding practices. Its solutions, DVT Eclipse IDE, DVT Debugger, Verissimo SystemVerilog Testbench Linter, and Specador Documentation Generator have been adopted worldwide. AMIQ strives to deliver high quality solutions and customer service responsiveness. For more information about AMIQ EDA and its solutions, visit and