AMIQ Releases the Automated UVM Compliance-Checking Capability

October 6, 2010, Sophia Antipolis, France — AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification, today announced the availability of the Universal Verification Methodology (UVM) Compliance Checker in the Design and Verification Tools (DVT) platform. The addition of this new capability is in line with AMIQ's efforts to support the universal verification IP (VIP) interoperability introduction. It also comes to expand the Open Verification Methodology (OVM) to UVM migration wizard, which was released by the company a few months ago.

The DVT platform is a modern and powerful programming environment for the Verilog, SystemVerilog and e design and verification languages. Based on the IDE approach, it integrates in a single window a smart code editor with various tools and components, including a class browser, linter, revision control, and task tracking. DVT supports the UVM libraries and guidelines and enables verification engineers to take advantage of all major features of the UVM.

Through the UVM compliance-checking capability, the DVT IDE helps engineers to automate the process of checking VIP against the UVM Compliance Checklist. With this tool, now they can effortlessly and consistently apply the UVM rules and ensure compliance to the official UVM SystemVerilog User Guide.

"Building on the incredible success of the Open Verification Methodology, the Universal Verification Methodology is critical to enable users to write scalable and portable verification IP", said Cadence Distinguished Engineer Michael Stellfox. "The complexity of SoC Verification faced by customers today requires more stringent adherence to the UVM reuse verification methodology in order to ensure more seamless IP integration. Capabilities like AMIQ's DVT UVM Compliance Checker are essential for customers to check that their verification IP is consistent with the UVM in order to accelerate time to SoC and silicon realization."

The UVM compliance-checking feature can be accessed in both batch and GUI mode. As an extension to this capability, DVT also provides automatic checklist update while fixing errors, direct jump to problematic source code, and an UVM Compliance HTML Report. In addition to these, DVT includes other features that simplify the development of UVM compliant code and speed verification. These include: UVM Smart Log, UVM Field Editor, and UVM Inline Documentation.

AMIQ is exhibiting at the 13th edition of the Sophia Antipolis Microelectronics Forum (SAME), on October 6 - 7, 2010, in France. The forum visitors can see a demonstration of the new UVM compliance-checking capability by visiting AMIQ at Booth #22.


AMIQ focuses on adding value to the verification domain through its proprietary tools and over 10 years of expertise in ASIC functional verification and reusable IP development. AMIQ provides the Design and Verification Tools (DVT™) platform, the first integrated development environment (IDE) for e and SystemVerilog. Powerful, yet easy to use, the DVT platform integrates in a single window a smart code editor with a complete suite of tools such as class browser, linter, revision control, and task tracking. It works with all major simulators and supports popular verification methodologies like OVM/UVM and VMM. The DVT IDE enables efficient code writing, simplifies the maintenance of reusable libraries and legacy code, and allows verification engineers to easily navigate through a project, making their work much easier and efficient. More information is available at

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