Dragan Labalo

I am a signal processing engineer defining the DSP specs for the RTL designers. Through the process of design verification I interact with digital verification team and RTL designers. I am not fluent in System Verilog and UVM framework, but in case the test bench does not match the specification I often need to look into the test bench and the RTL implementation and run and tweak the tests and design myself. DVT Eclipse IDE provides exceptional help for me to quickly navigate the design, reference C++ models and understand the hierarchy of the design and the UVM test bench. Highly recommended productivity tool.