Articles
Achieving the Interactive Development of Low-Power Designs
DVT Eclipse IDE can be used to develop RTL and power intent files in parallel, keeping them in lockstep as both evolve
Delivering on the Advanced Refactoring of Design and Verification Code
Refactoring makes code more readable and more maintainable, while making it more efficient for simulation and synthesis
Automatic Documentation Generation for RTL Design and Verification
Specador produces professional-looking documentation, with different fonts and styles, hyperlinks, and generated diagrams
Take Advantage of the Automated Refactoring of Design and Verification Code
Automatic refactoring provides an effective way to convert all code to a common format and produces more compact code
Correct Design and Verification Coding Errors as You Type
The auto-correct-as-you-type capability of DVT Eclipse IDE not only finds problems, but also proposes solutions
Cadence Delivers Portable Test and Stimulus Methodology and Library
AMIQ EDA used DVT Eclipse IDE to check the Cadence PSS System Methodology Library (SML) for compliance to the standard
An Important Next Step for Portable Stimulus Adoption
DVT Eclipse IDE has the ability to analyze the stimulus being specified in a PSS model and display possible scenarios
A Helping Hand for Design and Verification
Design and verification engineers need all the help they can get from hyperlinks, auto-complete, and task-specific wizards
Why Hyperlinks are Essential for HDL Debugging
Design and verification engineers need a modern IDE that performs sophisticated analysis and navigates in a flexible GUI
With Great Power Comes Great Visuality
Since DVT Eclipse IDE supports both UPF/IEEE 1801 and CPF, SoC teams can choose their preferred power intent format