Events
DVCon 2012 Cadence Verification Alliance Interview: "Verissimo SystemVerilog Testbench Linter "
"At DVCon 2012, long time Cadence Connections Partner AMIQ launch new product -- the "Verissimo" SystemVerilog testbench linter is optimized for functional verification with UVM, and supports users adding their own custom rules. In this video AMIQ's CEO Cristian Amitroaie reviews the highlights of this exciting new offering."
Users rate 29 more tools shown at DAC'11
It was the odd side niche tools like Amiq DVT Eclipse, Atrenta Spyglass, Duolog Bitwise, that caught user's mindshare in the Verilog/VHDL simulation space.
Anonymous:
Amiq DVT Eclipse for 'e' and System Verilog: I had not realized that I had been developing code by banging rocks together.
Ben Cohen, well known author of VHDL and SVA books:
I have been playing with this editor. It is tailored for System Verilog and particularly for OVM/UVM. It's extremely powerful is time saving.
This tool was clearly developed by users themselves (not just requirement people).
DVT Eclipse does dynamic code check on the fly, linting for SystemVerilog and linting for OVM/UVM, choice of editors (e.g., emacs), does context sensitive references to where objects are used, templates, OVM/UVM compliance checks with warnings and error IDs and links to them, auto macro inclusion on selected preferences, class diagram creation with options of details, links to user define tags in code.
It's very VERY powerful and is a great aid in development/debugging of design and verification code (and not just for SystemVerilog, as it also supports VHDL.
