Understanding UVM verification environments using DVT Eclipse IDE

Overview

This video presents visualization techniques, fast and precise navigation and search capabilities, as well as smart automated code completion in DVT Eclipse IDE to help you using UVM.

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This video was shot using DVT 20.1.25

Details

Large UVM projects are often hard to understand and even harder to debug without the proper tools. The DVT Eclipse IDE can help you employ visualization techniques, fast and precise navigation and search capabilities, as well as smart automated code completion.

Using the UVM Browser View

A good starting point for exploring any UVM project in DVT is the UVM Browser View. It shows UVM-based classes grouped by category: agents, drivers, monitors, and so on. If you want to focus on classes under a specific package, press Group by Package. At the bottom of the view, you can see the UVM-related API, like TLM ports, UVM flow-specific function overrides, and factory-registered class variables.

Editing UVM Factory Registration

When it comes to UVM factory registration, DVT does more than just showing you where variables are declared. Let's take this apb_transfer sequence item, for example, and delete all the macros. Now, right-click and go to Source > UVM Field Editor. From the apb_transfer class, select all the fields. For master and slave, let's also add the UVM_NO_COMPARE operation, and press OK. DVT generates the registration macros for all the selected fields and automatically detects the required field registration macro depending on the field type. If you want to edit an already existing registration, you can proceed in a similar manner.

Using the UVM Sequence Tree View

Another useful feature that you can easily trigger from the UVM Browser View is the UVM Sequence Tree. Search for a sequence of your choice, right-click, and select Show UVM Sequence Tree. This view presents the call hierarchy for a sequence, showing all the sub-sequences and transfers driven by it. For easier understanding, DVT collects all the comments associated with tree elements. Double-click on a sequence to go to its starting point. Select any element from the UVM Sequence Tree, and the Inspect view will show you detailed information.

Visualizing UVM Registers with Bifield Diagrams

Select any register operation to show the UVM Bitfield Register Diagram. It allows you to visualize the configuration of any uvm_reg in your project. The diagram can also be triggered by selecting a register in the UVM Browser View, or by placing the cursor over a register in the editor. To save it, simply right-click in the Inspect view and select Save As.

Using the Verification Hierarchy View

So far, we've seen how you can understand the UVM structure of your project using DVT features. Now let's switch to the Verification Hierarchy View to see how all these UVM components are linked together inside the test. Press the Select Top button and choose a test. Note how the view gets populated with the UVM testbench hierarchy.

Select any instance in the tree to see its TLM ports in the ports panel. Double-click an instance to go to the type_id::create() call. Double-click a port to go to its declaration.

Navigating with the Verification Breadcrumb

The Verification Breadcrumb on top of the editor shows you the path to the verification element starting from the verification top. If multiple paths are available, you can switch between them by pressing the Select Instance button. Click the arrow to the side of any verification element to see its child instances.

Right-click on a breadcrumb element to:

  • Open the Create Call
  • Open the Field Declaration
  • Copy the Hierarchy Path
  • Show the UVM Components Diagram

This diagram can also be triggered from the Verification Hierarchy View.

Visualizing Testbench Structure with UVM Component Diagrams

The diagram shows the UVM component containment and the TLM port connections. For detailed information about each of the elements in the diagram, use the Inspect panel. To customize the looks of the diagram, you can either increase the depth to see more details, or you can create filters to emphasize different UVM components in your diagram. A default filter allows you to color differently monitors and drivers, and you can easily use it as a template for creating your own. Right-click on the diagram elements to see the available actions. Press on Save As if you want to save the diagram for documentation purposes.