Press Releases
Munich, Germany
AMIQ EDA Introduces New Capabilities in Its Verissimo SystemVerilog Testbench Linter
AMIQ EDA announced the release of new capabilities for dead code analysis and improved reporting of Pass/Fail checks in its Verissimo SystemVerilog Testbench Linter - a static code analysis tool for the SystemVerilog language and Universal Verification Methodology (UVM). The newly introduced capabilities enable engineers to further improve code performance and testbench reliability and reduce maintenance costs.
San Francisco, California
AMIQ EDA Launches Specador Documentation Generator for e Language, SystemVerilog, Verilog, and VHDL Projects
AMIQ EDA launches Specador Documentation Generator, a tool that automatically generates accurate HTML documentation from comments inserted in the source code, enabling design and verification engineers to effortlessly generate and maintain well-organized documentation.
San Jose, California
AMIQ EDA Releases Version 3.5 of the Design and Verification Tools (DVT) IDE
AMIQ EDA announces version 3.5 of its flagship solution - DVT Eclipse IDE. The new version provides enhanced compilation, improved UVM support, and a streamlined GUI to help design and verification engineers increase code development quality and productivity. It also offers a set of capabilities that simplifies DVT deployment.
Bucharest, Romania
AMIQ EDA Announces Full Cross-Language Capabilities for Mixed-Language Projects
AMIQ EDA releases full cross-language capabilities for mixed-language projects in its flagship solution - Design and Verification Tools (DVT) IDE. Continuing to focus on improving productivity, AMIQ added these new capabilities to enhance cross-language integration and enable design and verification engineers to work easily on projects that include source code written in multiple languages, particularly SystemVerilog, Verilog and VHDL.
San Francisco, California
AMIQ Releases New Design-Oriented Features in the DVT IDE
AMIQ EDA releases new design-oriented features in its Design and Verification Tools (DVT) IDE. These features enable design engineers to easily understand how a signal propagates in a design, connect two modules across the design hierarchy, and inspect and document a module structure.
Bucharest, Romania
AMIQ Has a New Logo
AMIQ EDA and AMIQ Consulting announce they have new logos. The new logos better represent the values and directions of development of the two companies: AMIQ EDA, founded in 2008 with a focus on design and verification tool development and AMIQ Consulting, founded in 2003, which provides verification consulting services.
San Jose, California
Ensure an Effective Audit and Best Coding Practices with AMIQ's Verissimo SystemVerilog Testbench Linter
AMIQ EDA announces the release of the Verissimo SystemVerilog Testbench Linter, a static code analysis tool that enables engineers to perform an effective audit of their testbenches and meet the requirements of today's complex verification environments. Verissimo helps identify improper SystemVerilog language, semantics, and styling usage, as well as verify the compliance with the UVM guidelines.
Munich, Germany
New Advanced e Language Debugging Capability in DVT to Boost Verification Productivity
AMIQ announces the DVT e-Debug Add-On module as an extended capability of the DVT Eclipse IDE, to provide advanced debugging capabilities for the e language users. The DVT e-Debug module integrates seamlessly with Cadence® Incisive® Enterprise Simulator.
Sophia Antipolis, France
AMIQ Releases the Automated UVM Compliance-Checking Capability
AMIQ EDA announces the new UVM compliance-checking capability in the DVT IDE to help engineers automate the process of checking VIP against the UVM Compliance Checklist and consistently apply the UVM guidelines when building their verification environments.
Anaheim, California
BigBand Networks Adopts AMIQ's DVT to Shorten Its Verification Schedules
BigBand Networks, Inc. (NASDAQ: BBND), a provider of broadband services and innovative digital video networking solutions has adopted AMIQ's DVT IDE for the e language (eDT) to enhance the efficiency in hardware verification.