Press Releases
San Jose, California
AMIQ EDA Joins OpenHW Group and Contributes Linting Capabilities for CORE-V Open-Source RISC-V Cores and Testbenches
“Simulators and other electronic design automation (EDA) tools detect some types of coding errors, but the OpenHW team was looking for a dedicated linting tool with more capabilities,” said Cristian Amitroaie, CEO of AMIQ EDA. “Our solution detects many types of issues, checking more than 700 rules for SystemVerilog and the Universal Verification Methodology (UVM), and offers suggestions for resolving them. Developers and users of OpenHW Group testbenches can be certain that their code is correct and follows industry best practices.”
Bucharest, Romania
AMIQ EDA Achieves ISO 9001 Quality Standard Certification
We are proud of our product development flow and other processes, and we continually strive for the highest quality.
San Jose, California
AMIQ EDA Updates UVM Rule Checks for Latest Release of the Universal Verification Methodology Standard
“The UVM, like many standards, evolves significantly with each new version,” said Cristian Amitroaie, CEO of AMIQ EDA. “We are pleased to ensure that our users remain compliant by avoiding outdated aspects of the API while helping them to use new functionality quickly and easily.”
San Jose, California
AMIQ Consulting Wins Third Place Stuart Sutherland Best Paper Award at DVCon U.S.
Open-Source Framework for Co-Emulation Using PYNQ” has received the Stuart Sutherland Best Paper third place award at the Design and Verification Conference (DVCon) U.S. Ioana Catalina Cristea and Dragos Dospinescu of AMIQ Consulting co-authored the paper and presented the results at the virtual conference.
San Jose, California
AMIQ EDA Announces Solution for Continuous Integration of SystemVerilog Testbenches
“Verissimo and DVT Eclipse are being used across Arm in continuous integration flows to help better identify problems in coding and assess project status,” said Tran Nguyen, Director of Design Services, Arm. “The precise feedback helps with coding discipline across large project teams and enables us to deliver optimized designs for a wide range of users.”
San Jose, California
AMIQ EDA Rearchitects Design Elaboration Engine for Faster Performance and Greater Accuracy
AMIQ EDA today announced that it has overhauled the design elaboration engine in its flagship Design and Verification Tools (DVT) Eclipse IDE to handle much larger and more complex system-on-chip (SoC) projects.
San Jose, California
AMIQ EDA Sponsors DVCon Best Paper and Poster Awards and Congratulates Winners
We congratulate the Best Paper and Poster winners from the 2020 Design and Verification Conference and Exhibition U.S. (DVCon U.S.) held in San Jose. The awards are voted by conference attendees.
San Jose, California
AMIQ EDA Releases Version 20.1 of the Design and Verification Tools Eclipse IDE
AMIQ EDA announced version 20.1 of its flagship solution the DVT Eclipse IDE. The new version includes important new features for developing, viewing, and maintaining complex hardware description language (HDL) designs.
San Jose, California
AMIQ EDA Announces Advanced Comparison and Filtering Capabilities for Analysis of Testbench Coding Violations
AMIQ EDA today announced that the latest release of its Verissimo SystemVerilog Testbench Linter includes advanced features for comparing reports of rule violations and intelligently filtering the results. This yields much less time spent in examining lint reports and debugging reported violations, speeding verification and reducing project duration.
San Jose, California
AMIQ EDA Announces its Verissimo SystemVerilog Testbench Linter Supports Auto-Correction
AMIQ EDA today announced that the latest release of its Verissimo SystemVerilog Testbench Linter includes the ability to automatically correct violations found for certain classes of coding rules.