Articles
Giving AI Agents Access to a Compiled Design and Verification Database
We started to wonder whether other tools, specifically AI agents, could benefit if they had access to project information within our internal database. It turned out that there is an open industry standard called Model Context Protocol (MCP) that serves exactly this purpose. It’s designed to connect AI agents to external data and applications. The goal is to make AI results more accurate by providing access to specialized or application-specific knowledge that was not learned through general training.
2026 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
We’re integrating more AI-enabled features to further help our users create and debug design and verification code. We’re also working on ways to provides access to our internal models for both IDE users and AI developers. In addition, we’re adding AI features to both Verissimo SystemVerilog Linter and Specador Documentation Generator.
Runtime Elaboration of UVM Verification Code in DVT IDE
DVT IDE actually performs a “run 0” internally to allow all the UVM elaboration to happen. We call this process UVM runtime elaboration to reflect its non-static nature.
11 Myths About the Portable Stimulus Standard
Is the Portable Stimulus Standard (PSS) living up to its promise of portable verification and validation across levels of hierarchy and platforms?
SystemVerilog Macro Debugging and Refactoring: From Legacy Code to Maintainable Modern Design Patterns
Learn how to debug and refactor complex SystemVerilog macros. Examples and tools that help replace legacy code with more maintainable design patterns.
Refactoring Tactics for Cleaner RTL and Faster Simulation in Verilog and SystemVerilog
Learn how refactoring improves your Verilog and System Verilog code. Tactics and tools to accelerate simulation, improve RTL, and simplify maintenance.
AMIQ EDA at the 2025 Design Automation Conference
The new AI Assistant feature in the Design and Verification Tools IDE family simplifies code generation and modification using a large language model. DVT IDE now includes over 30 new code checks to ensure code quality and improved testbench elaboration time. Verissimo's linter adds around 60 new rules each year, with fast incremental linting capabilities for user convenience.
2025 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
Our most exciting innovation for the year was our first incorporation of artificial intelligence (AI) Into our products. As Serban Ionica discussed in October, AI Assistant is included for no extra cost in the latest releases of DVT IDE for Visual Studio (VS) Code and DVT Eclipse IDE. It works with any large language model (LLM) to generate new design or verification code and to explain and improve existing code. The results are much better than with a general-purpose AI tool because we leverage our project database and its deep knowledge about your design and testbench. Users are telling us that we have really improved their coding and debug efficiency.
Adding an AI Assistant to a Hardware Language IDE
AI Assistant a new feature of our DVT IDE family that helps hardware engineers be even more productive when developing code for the design and verification of complex chips. The knowledge contained in LLMs, when combined with our own insight into the design and testbench, enables users to generate, modify, and understand code more easily.
Writing Better Code More Quickly with an IDE and Linting
Verissimo has caught some tricky variable bit width issues where a macro hid that only the lowest order bit was being compared. Both DVT IDE and Verissimo also save a lot of time. In the past, we found that when we wrote or edited code we spent too much time in a compile-debug-fix loop until it was clean. This happened hundreds, maybe thousands, of times on every project. With the ability to find and fix errors interactively within the IDE, that loop is significantly shorter. We get great team style alignment, with more efficient code reviews. So clearly we save many weeks of effort.