Articles
Improving Verification of Battery Cell Monitoring Chips
Dukosi, whose Cell Monitoring System is revolutionizing the performance, safety, and sustainability of high power batteries used in many applications, are a user of AMIQ EDA’s products, so I had a nice chat with Anders Convery, their Senior Principal Verification Engineer.
Autocomplete in Verilog and SystemVerilog: How Semantic and AI-Assisted Code Completion Save Time and Improve Accuracy
Learn how text-driven, semantic-aware, and AI-assisted autocomplete improve RTL and UVM development in Verilog and SystemVerilog projects.
Giving AI Agents Access to a Compiled Design and Verification Database
We started to wonder whether other tools, specifically AI agents, could benefit if they had access to project information within our internal database. It turned out that there is an open industry standard called Model Context Protocol (MCP) that serves exactly this purpose. It’s designed to connect AI agents to external data and applications. The goal is to make AI results more accurate by providing access to specialized or application-specific knowledge that was not learned through general training.
2026 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA
We’re integrating more AI-enabled features to further help our users create and debug design and verification code. We’re also working on ways to provides access to our internal models for both IDE users and AI developers. In addition, we’re adding AI features to both Verissimo SystemVerilog Linter and Specador Documentation Generator.
Runtime Elaboration of UVM Verification Code in DVT IDE
DVT IDE actually performs a “run 0” internally to allow all the UVM elaboration to happen. We call this process UVM runtime elaboration to reflect its non-static nature.
11 Myths About the Portable Stimulus Standard
Is the Portable Stimulus Standard (PSS) living up to its promise of portable verification and validation across levels of hierarchy and platforms?
SystemVerilog Macro Debugging and Refactoring: From Legacy Code to Maintainable Modern Design Patterns
Learn how to debug and refactor complex SystemVerilog macros. Examples and tools that help replace legacy code with more maintainable design patterns.
Better Automatic Generation of Documentation from RTL Code
Specador makes it possible for design and verification engineers to easily create and maintain proper and well-organized documentation.
Refactoring Tactics for Cleaner RTL and Faster Simulation in Verilog and SystemVerilog
Learn how refactoring improves your Verilog and System Verilog code. Tactics and tools to accelerate simulation, improve RTL, and simplify maintenance.
AMIQ EDA at the 2025 Design Automation Conference
The new AI Assistant feature in the Design and Verification Tools IDE family simplifies code generation and modification using a large language model. DVT IDE now includes over 30 new code checks to ensure code quality and improved testbench elaboration time. Verissimo's linter adds around 60 new rules each year, with fast incremental linting capabilities for user convenience.