Tom Anderson
Runtime Elaboration of UVM Verification Code in DVT IDE
DVT IDE actually performs a “run 0” internally to allow all the UVM elaboration to happen. We call this process UVM runtime elaboration to reflect its non-static nature.
11 Myths About the Portable Stimulus Standard
Is the Portable Stimulus Standard (PSS) living up to its promise of portable verification and validation across levels of hierarchy and platforms?
Refactoring Tactics for Cleaner RTL and Faster Simulation in Verilog and SystemVerilog
Learn how refactoring improves your Verilog and System Verilog code. Tactics and tools to accelerate simulation, improve RTL, and simplify maintenance.
Integrated Development Environment (IDE) for Hardware Design and Verification
Learn what a hardware IDE is and how it works, its role in accelerating HDL design and verification, and how it differs from editors, compilers, and simulators.
What Is RISC-V & How Does It Work?
Learn what RISC-V is, its benefits and limitations. 101 guide on why is this open-source ISA so popular that it's reshaping processor design.
Adding an AI Assistant to a Hardware Language IDE
AI Assistant a new feature of our DVT IDE family that helps hardware engineers be even more productive when developing code for the design and verification of complex chips. The knowledge contained in LLMs, when combined with our own insight into the design and testbench, enables users to generate, modify, and understand code more easily.
Writing Better Code More Quickly with an IDE and Linting
Verissimo has caught some tricky variable bit width issues where a macro hid that only the lowest order bit was being compared. Both DVT IDE and Verissimo also save a lot of time. In the past, we found that when we wrote or edited code we spent too much time in a compile-debug-fix loop until it was clean. This happened hundreds, maybe thousands, of times on every project. With the ability to find and fix errors interactively within the IDE, that loop is significantly shorter. We get great team style alignment, with more efficient code reviews. So clearly we save many weeks of effort.
Delivering Three Key Aspects of IP Quality
There are three main requirements to IP quality. The most obvious is functional correctness, another is IP robustness, and last but not least, IP maintainability. AMIQ EDA has products that help you meet such requirements.
11 Myths About Integrated Development Environments
IDEs were introduced to improve the efficiency and accuracy of writing and maintaining code, providing easier file navigation, hierarchical views of the project codebase, etc. However, myths have arisen about IDEs, and this article looks to clear the air.
Making Power Intent Specification Easy
By supporting power intent formats, the same IDE used for design and verification code can ensure consistency across all files