Filtering by Element Type

The element-type tag allows you to identify elements introduced by a particular language construct, like functions, fields or structs. The table below exemplifies what language constructs map to the available element types.

Element Types	SV	VHDL	E
ACTION
ACTIVITY
ALIAS		alias alias_name is alias_type;
ARCHITECTURE		architecture architecture_name of entity_name is begin end architecture;
ASSERT	assert_name : assert property(…); cover_name : cover property(…); assume_name : assume property(…);		assert boolean != FALSE;
BLOCK	initial begin … end	blk_name : block … begin … end block;
CHECK			check check_name that …;
CHECKER	checker checker_name(…); endchecker
CHECKER_INSTANCE	checker_name checker_instance(…);
CLASS	class class_name; endclass
CLOCKING_BLOCK	clocking clocking_block_name @(…); endclocking
COMPONENT		component … end component;
CONFIGURATION	config config_name; endconfig	configuration config_name of entity_name is … end configuration;
CONSTRAINT	constraint constraint_name{ … }		keep constraint_name is … ;
COVER_CROSS	cross_name : cross item_name, … ;		cross kind using … ;
COVER_GROUP	covergroup covergroup_name; endgroup		cover cover_name is { … };
COVER_POINT	coverpoint_name : coverpoint variable_name;		item kind using … ;
COVER_TRANSITION			transition transition_name using … ;
ENTITY		entity entity_name is end entity;
EVENT	event event_name;		event event_name;
EXEC_BLOCK
EXPECT	expect_name: expect ( … ) else … ;		expect expect_name is …
FIELD	field_type field_name;		field_name : field_type;
FUNCTION	function return_type function_name(…); endfunction	function function_name( … ) return return_type;
GENERATE_BLOCK	generate … endgenerate genvar i; for ( … ) begin end	label: for … in … to … generate end generate;
INSTANCE	modport_name instance_name( … ); user_defined_primitive instance_name( … ); logic_gate instance_name( … );	label_name : component_type PORT MAP ( … ); label_name : component_type GENERIC MAP ( … );
INTERFACE	interface interface_name; endinterface
INTERFACE_INSTANCE	interface_name interface_instance();
LIBRARY	+dvt_init -work lib_name	+dvt_init -work lib_name
LINKAGE
MACRO	`define macro_name macro_value		define macro_name macro_value;
METHOD			method_name() is { … };
METHOD_TYPE			method_type method_type_name ();
MODPORT	modport modport_name(…);
MODULE	module module_name(…); endmodule
MODULE_INSTANCE	module_name mod_instance(…);
NAMESPACE
ONEVENT			on event_name { … }
PACKAGE	package package_name; endpackage	package package_name is end package;	package package_name;
PACKAGE_BODY		package body package_body_name is end package body;
PACKAGE_INSTANCE		package instance_name is new package_name;
PARAMETER	parameter parameter_name;
PORT	output port_name; input port_name; real port_name;	port (…);
PRIMITIVE	primitive primitive_name(…); endprimitive
PROCESS		process (…) is begin end process;
PROGRAM	program program_name (…); endprogram
PROGRAM_INSTANCE	program_name instance_name(…);
PROPERTY_SEQUENCE	property property_name; endproperty sequence sequence_name; endsequence	property property_name is … ; sequence sequence_name is … ;
SIGNAL		signal signal_name : signal_type;
STRUCT			unit unit_name { … }; sequence sequence_name using … ; struct struct_name { … };
SUBPROGRAM_INSTANCE		function instance_name is new function_name; procedure instance_name is new procedure_name;
TASK	task task_name(); endtask
TOKEN
TYPE	typedef int unsigned uint; typedef struct { … } struct_name; typedef enum { … } enum_name;	type type_name is (…);	type type_name : type;
TYPE_PARAMETER	class class_name #(type type_name=bit); endclass
TYPEDEF
UNION
VARIABLE		variable var_name: var_type; generic (var_name : var_type);
VUNIT		vunit vunit_name(entity_name(architecture_name)) { … }