Vertical Alignment

When enabled, this option performs vertical alignment.

• Vertical Alignment Tokens (DVT.textEditor.vHDL.formatting.verticalAlignment.verticalAlignTokens)

The lines of code inside the same scope are aligned by the specified list of vertical alignment tokens. Vertical alignment is performed left to right, by the same token. For example, assuming = and : as vertical alignment tokens: In order to use the comma character , as a vertical alignment token, the character must be preceded by the escaping character \.

Before	After (“:=,:” tokens)

• Only Consecutive Lines (DVT.textEditor.vHDL.formatting.verticalAlignment.onlyConsecutiveLines) - Controls whether vertical alignment is applied only to consecutive lines.

Before	After

• Vertical Align Single Line Comments (DVT.textEditor.vHDL.formatting.verticalAlignment.verticalAlignSingleLineComments) - Controls whether single line comments are vertically aligned.

Before	After

• Vertical Align To Open Parenthesis (DVT.textEditor.vHDL.formatting.verticalAlignment.verticalAlignToOpenParenthesis) - Controls whether to vertically align relative to open parenthesis.

Before	After

Vertical Align Patterns (DVT.textEditor.vHDL.formatting.verticalAlignment.verticalAlignPatterns)

• Constant Declarations (VhdlConstantDeclarations) - Controls whether to align constant declarations.

Before	After

• Port Declarations (VhdlPortDeclarations) - Controls whether to align port declarations.

Before	After

• Record Declarations (VhdlRecordDeclarations) - Controls whether to align record declarations.

Before	After

• Signal Declarations (VhdlSignalDeclarations) - Controls whether to align signal declarations.

Before	After

• Variable Declarations (VhdlVariableDeclarations) - Controls whether to align variable declarations.

Before	After

• Variable, Signal, Constant Declarations (VhdlVariableSignalConstantDeclarations) - Controls whether to align variable, signal and constant declarations.

Before	After