The Code Factory allows you to easily generate instances, signals and testbenches starting with modules or entities.
Factory Input
It is required that you first set an input. Right-click on the element definition and select from the context menu the option
Set Factory Input under
Code Factory.
The current input persists until a new one is set or until a full build is invoked.
Note: The input can be either a SystemVerilog module, interface, program, checker or a VHDL entity.
Creating code
Having set an input, you can do one of the following:
Create Instance for instantiating the design element;
Create Signals for listing the ports of the design element as signals;
Create Testbench for defining a testbench that instantiates the design element with all the required port connections already made;
Create Component for defining a component (VHDL only)
Create WaveDrom Diagram for defining a
WaveDrom timing diagram description stub
Create from Custom Template
The code will be inserted at the cursor's current position.
Any information or errors during Code Factory operations are shown in the status bar.
Notes
Create from Template
You can customize the output of the Code Factory using
FreeMarker Templates. API is available on the FreeMarker model root.
In the script template you can access structured data describing the design which has been set as factory input. The design is represented by the model
root.
The following API is accessible in the FreeMarker template:
Design API
Port API
port.getDirection()
port.getData(): returns the port data (see port data API below)
port.isInterfacePort()
port.isGenericInterfacePort()
port.getInterface(): returns the interface for interface ports
Port Data API
portData.getType()
portData.getNetType()
portData.hasPackedDimension()
portData.getPacketDimension()
portData.hasUnpackedDimension()
portData.getUnpackedDimension()
portData.hasSign()
portData.getSign()
Parameter API
Example
<#assign module = root>
<#assign max_port_name_chr = 0>
<#assign max_port_type_chr = 5>
<#--Determine the max length for ports -->
<#if module.hasPorts()>
<#list module.getPorts() as port>
<#assign port_name_chr = (port.getName())?length>
<#if max_port_name_chr < port_name_chr>
<#assign max_port_name_chr = port_name_chr>
</#if>
<#assign port_type_chr = (port.getData().getType())?length>
<#if max_port_type_chr < port_type_chr>
<#assign max_port_type_chr = port_type_chr>
</#if>
</#list>
</#if>
<#--print ports -->
<#if module.hasPorts()>
<#list module.getPorts() as port>
<#assign port_name = r"${" + port.getName() + "}">
<#assign pad = max_port_name_chr + 3>
<#assign data = port.getData()>
<#assign type = data.getType()?lower_case>
<#if !(type?has_content)>
<#assign type = "logic">
</#if>
${type?right_pad(max_port_type_chr) + " " + port_name?right_pad(pad) + ";"}
</#list>
</#if>
Note: More examples are available in the Code Factory predefined project (DVT Examples > Misc > Code Factory)
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