28.5.2 Component Diagrams from SimulationTo generate the Component Diagrams from simulation, some additional arguments must be added to the build directives, depending on the simulator. IUS: "-f $DVT_HOME/libs/dvt_chs/dvt_chs.top.ius.f". When using -makelib/-endlib add "-f $DVT_HOME/libs/dvt_chs/dvt_chs.ius.f" inside the library and "-top dvt_chs_module" outside of it. VCS: "-f $DVT_HOME/libs/dvt_chs/dvt_chs.vcs.f" Questa: "-f $DVT_HOME/libs/dvt_chs/dvt_chs.questa.f"
NOTE: To generate diagrams for OVM environments, use the appropriate filelist from $DVT_HOME/libs/dvt_chs/ovm
When the simulation starts, a
component_hierarchy_of_<test_name>.chd will be generated in the working directory.
Open the generated file in DVT to inspect the diagram.
The location of the diagram can be changed by setting the
DVT_CHS_FILE environment variable before running the simulation.
export DVT_CHS_FILE=/path/to/a/components_diagram.chd # sh, bash
setenv DVT_CHS_FILE /path/to/a/components_diagram.chd # csh, tcsh
You can stop the test immediately after the diagram has been generated by setting the
DVT_CHS_STOP_TEST environment variable before running the simulation.
export DVT_CHS_STOP_TEST=true # sh, bash
setenv DVT_CHS_STOP_TEST=true # csh, tcsh
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