DVT SystemVerilog IDE User Guide
Rev. 24.2.25, 31 October 2024

4.7.7 questa.qrun Compatibility Mode

The +dvt_init+questa.qrun directive resets the builder to the questa.qrun default state.

Syntax Extensions
Verilog 1995.v95, .v95p
Verilog 2001.v, .vp, .vs
System Verilog 1800-2012.sv, .svp, .svi, .svh, .vlib, .vcfg, .pslvlog
VHDL 1987.vhd, .vhdl, .vhdp, .vhdlp
VHDL 2008.pslvhdl, .vhcfg
C/c++.c, .h, .cc, .cpp, .cxx

Language Syntax for Unmapped Extensions: Skip

Language Syntax for Included Files: Included files are parsed using the syntax that was used for parsing the including file.

Mode Specific Directives

Directive Description
-2002Enable support for VHDL 2002
-2008Enable support for VHDL 2008
-87Enable support for VHDL 87
-93Enable support for VHDL 93
-cuname <compilation_unit_name>Compile under <compilation_unit_name> package; the directive is enforced until:


* another -cuname directive is encountered


* +dvt_init directive is encountered


* end of default.build is encountered
-defaultHDLCompiler=<vlog/vcom>All files that would be parsed according to the Language Syntax for Unmapped Extensions will be parsed with Verilog 2001 if vlog option is selected or VHDL 87 for vcom option.
-defineall <DEFINE_NAME>=<replacement>Define a preprocessing symbol for SystemVerilog and C/C++. The replacement is optional. You may quote the replacement with ticks (') or quotes ("). If defined, environment variables are expanded.
-f <filename>Specify a <filename> containing command line arguments
-makelib <lib_name>


-makelib /path/to/ <lib_name>


-makelib /some/path: <lib_name>


... -endlib
Compiles files specified inside a - makelib ... - endlib section into the <lib_name> library. Files in makelib sections are compiled before files in the enclosing invocation. Directives in the makelib section only apply to the makelib section files. Directives in the enclosing invocation apply to all files in the invocation. The - work directive is ignored within a makelib section.
-pa_upf <upf_file>Specify a Unified Power Format file to be analyzed.
-reflib <lib>Specify the library search order for Verilog packages. You can specify multiple libraries by using this option multiple times.
-svParse files with unmapped extensions as SystemVerilog
-sv05compatUse SystemVerilog 2005 syntax flavor
-sv09compatUse SystemVerilog 2009 syntax flavor
-sv12compatUse SystemVerilog 2012 syntax flavor
-svfilesuffix=<ext1> ,<ext2>... All files with <ext1>, <ext2>, ... extensions are parsed as SystemVerilog
-sysc <c/c++ source files and options> -endAdd $SYSTEMC_HOME/src as C include dir. Falls back to $DVT_SYSTEMC_HOME if $SYSTEMC_HOME is not defined.
-top <design_unit>Specify a design top module or configuration name. You can specify multiple tops either by using the directive multiple times or by specifying multiple top names separated by the '+' character or a combination thereof.
-uvmDVT compiles the UVM library, in order of precedence, from: $UVM_HOME, $MTI_HOME/verilog_src/uvm-1.1d, $DVT_UVM_HOME, $DVT_HOME/predefined_projects/libs/uvm-1.2


If $MTI_HOME is not defined, it is inferred from the location of the vlog executable


If -L $MTI_HOME/<uvm_lib> is specified anywhere within the current invocation, then UVM is compiled from $MTI_HOME/verilog_src/<uvm_lib>


Whenever compiling UVM from $MTI_HOME, the $MTI_HOME/verilog_src/questa_uvm_pkg-1.2/ is also compiled
-uvmhome <path>If <path> is:


the word "default": equivalent with -uvm


an existing absolute path or relative path: load the UVM library from the specified <path>


Has precedence over -uvm.
-uvmexthome <path>If <path> is an existing absolute path or relative path: load the UVM extension files from the specified <path>.


Should be used in conjunction with '-uvmhome'.
-vlog01compatUse Verilog 2001 syntax flavor
-vlog95compatUse Verilog 1995 syntax flavor
-vlog.ext= +<ext> Files with <ext> extension will be parsed using the Verilog 2001 syntax flavor. If the optional + is specified, the mapping will be added to the default File Extension to Language Syntax Mapping. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default File Extension to Language Syntax Mapping will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - vlog.ext=+.svh,.svp. The dot (.) for specifying <ext> is mandatory.
-vcom.ext= +<ext> Files with <ext> extension will be parsed using the VHDL 87 syntax flavor. If the optional + is specified, the mapping will be added to the default File Extension to Language Syntax Mapping. Otherwise, the default mapping of the specified <syntax> is overridden. If you specify the override directive multiple times for the same <syntax>, the default File Extension to Language Syntax Mapping will be overridden only the first time. You can specify more extensions at once, comma-separated, for example - vcom.ext=+.svh,.svp. The dot (.) for specifying <ext> is mandatory.
-work <lib>Compile into library <lib>.
+UVM_TESTNAME=<testname>The name of the UVM test which will be automatically created under uvm_root.

Predefined API

QUESTADefined as preprocessing macro without value.
MODEL_TECHDefined as preprocessing macro without value.