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Regular Verilog/SystemVerilog File
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Linked Resource Verilog/SystemVerilog File See
Linked Resources.
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Out of Project Verilog/SystemVerilog File The file is not inside a project directory, nor accessible as a linked resource. Functionality is limited on "gray" files.
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Library
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Package
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Program
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Typedef
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Class
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Interface
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Module
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Checker
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Primitive
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Generate
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Field
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Enumeration name
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Constructor
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Function
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Task
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Event
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Fork/join - Indicates a fork block.
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Process - Indicates a process in a fork block.
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Constraint
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Cover Group
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Input Port
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Output Port
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Bidirectional Port
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Interface Port
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ModPort
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Port passed multiple times when tracing a signal
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Wire
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Port connection
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Always
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Assign
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Module Instance
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Unknown Instance
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Interface Instance
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Object Instance - Relevant for XVM methodologies, indicates a "created" object.
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Component Instance - Relevant for XVM methodologies, indicates a "created" component.
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Test Class - Relevant for XVM methodologies, indicates a "test" class.
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Sequence - Relevant for XVM methodologies, indicates a "sequence" class.
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Sequence Item - Relevant for XVM methodologies, indicates a "sequence item" class.
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Root Class - Relevant for XVM methodologies, indicates the "root" class.
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Preprocessing define
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Preprocessing undefine
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Preprocessing ifdef, ifndef
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Code Template For example in autocomplete proposals.
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