Preferences Keys

Formatting preferences are serialized as key-value pairs, by default under $HOME/.config/Code/User/settings.json.

Furthermore, an input file with the same format is used to configure Verissimo formatting rules, such as SVTB1.0.

Preference Name

Details

Preference Key

Default Value

Whitespace

Add Whitespace After

List of tokens after which whitespace will be added.

DVT.textEditor.systemVerilog.formatting.whitespace.addWhitespaceAfter

[]

Add Whitespace Before

List of tokens before which whitespace will be added.

DVT.textEditor.systemVerilog.formatting.whitespace.addWhitespaceBefore

[]

Compact Whitespace Groups

Controls whether to compact consecutive whitespace characters.

DVT.textEditor.systemVerilog.formatting.whitespace.compactWhitespaceGroups

false

Compact Consecutive Empty Lines

Controls whether to compact consecutive empty lines.

DVT.textEditor.systemVerilog.formatting.whitespace.compactConsecutiveEmptyLines

false

Maximum Number Of Consecutive Empty Lines

Maximum number of consecutive empty lines that can appear in a file.

DVT.textEditor.systemVerilog.formatting.whitespace.maximumNumberOfConsecutiveEmptyLines

1

Insert spaces

When enabled, indentation will use space characters, otherwise tabs will be used.

editor.insertSpaces

true

Remove New Line After

List of tokens after which new lines will be removed.

DVT.textEditor.systemVerilog.formatting.whitespace.removeNewLineAfter

[]

Remove New Line Before

List of tokens before which new lines will be removed.

DVT.textEditor.systemVerilog.formatting.whitespace.removeNewLineBefore

[]

Tab width

Controls the size of a tab in spaces.

editor.tabSize

4

Trim End of Line Whitespace

Controls whether to trim end of line whitespaces.

DVT.textEditor.systemVerilog.formatting.whitespace.trimEndOfLineWhitespace

true

Trim Whitespace Lines

Controls whether to trim lines containing only whitespaces.

DVT.textEditor.systemVerilog.formatting.whitespace.trimWhitespaceLines

true

Indentation

Add New Line After Begin And Before End

Controls whether to add a new line after begin and before end.

DVT.textEditor.systemVerilog.formatting.indentation.addNewLineAfterBeginAndBeforeEnd

false

Add New Line After End

Controls whether to add a new line after end.

DVT.textEditor.systemVerilog.formatting.indentation.addNewLineAfterEnd

false

Close Scope Macros

List of macros that close a scope and decrease the indentation of subsequent code.

DVT.textEditor.systemVerilog.formatting.indentation.closeScopeMacros

[]

Do Not Indent Single Line Comments At Beginning Of Line

Controls whether to indent single line comments starting at the beginning of a line.

DVT.textEditor.systemVerilog.formatting.indentation.doNotIndentSingleLineCommentsAtBeginningOfLine

true

Do Not Indent Multi-line Macro Definitions

Controls whether to indent multi-line macro definitions. This option is available only when the Preprocessing preference is set to Indent, Indent and increase indentation level, Indent and increase indentation level except first or Move at first column.

DVT.textEditor.systemVerilog.formatting.indentation.doNotIndentMulti-lineMacroDefinitions

false

Else

Controls the placement of else: Leave as is, On a new line, On the same line.

DVT.textEditor.systemVerilog.formatting.indentation.else

“Leave as is”

Enable More Parameters Per Line If Less Than

Controls whether to place parameters on the same line when their number does not exceed a certain value and the Parameters preference is set to One per line (open parenthesis on the same line) or One per line (open parenthesis on the next line).

DVT.textEditor.systemVerilog.formatting.indentation.enableMoreParametersPerLineIfLessThan

false

Ignore Lines Starting With

List of line prefixes matching lines that will be ignored while indenting.

DVT.textEditor.systemVerilog.formatting.indentation.ignoreLinesStartingWith

[]

Implicit Semi Macros

List of macros encapsulating semicolon or end delimiters.

DVT.textEditor.systemVerilog.formatting.indentation.implicitSemiMacros

 
["ovm_info()", "ovm_warning()",
"ovm_error()", "ovm_fatal()",
"ovm_create()", "ovm_create_on()",
"ovm_do()", "ovm_do_pri()",
"ovm_do_with()", "ovm_do_pri_with()",
"ovm_do_on()", "ovm_do_on_pri()",
"ovm_do_on_with()", "ovm_do_on_pri_with()",
"ovm_do_seq()", "ovm_do_seq_with()",
"ovm_send()", "ovm_send_pri()",
"ovm_rand_send()", "ovm_rand_send_pri()",
"ovm_rand_send_with()", "ovm_rand_send_pri_with()",
"ovm_do_callbacks()", "ovm_do_obj_callbacks()",
"ovm_do_task_callbacks()", "ovm_do_callbacks_exit_on()",
"ovm_do_obj_callbacks_exit_on()", "ovm_cb_trace()",
"ovm_cb_trace_noobj()", "uvm_info()", "uvm_warning()",
"uvm_error()", "uvm_fatal()",
"uvm_create()", "uvm_create_on()", "uvm_create_seq()",
"uvm_do()", "uvm_do_pri()", "uvm_do_with()",
"uvm_do_pri_with()", "uvm_do_on()", "uvm_do_on_pri()",
"uvm_do_on_with()", "uvm_do_on_pri_with()", "uvm_do_seq()",
"uvm_do_seq_with()", "uvm_send()", "uvm_send_pri()",
"uvm_rand_send()", "uvm_rand_send_pri()",
"uvm_rand_send_with()", "uvm_rand_send_pri_with()",
"uvm_register_cb()", "uvm_set_super_type()",
"uvm_do_callbacks()", "uvm_do_obj_callbacks()",
"uvm_do_callbacks_exit_on()", "uvm_do_obj_callbacks_exit_on()",
"uvm_cb_trace()", "uvm_cb_trace_noobj()"]

Indent Multi-line Assigns

Controls whether to indent multi-line assigns.

DVT.textEditor.systemVerilog.formatting.indentation.indentMulti-lineAssigns

true

Indent Multi Line Comments

Controls whether to indent multi-line comments.

DVT.textEditor.systemVerilog.formatting.indentation.indentMultiLineComments

true

More Parameters Per Line If Less Than

Maximum number of parameters that can appear on a line when Enable More Parameters Per Line If Less Than is enabled.

DVT.textEditor.systemVerilog.formatting.indentation.moreParametersPerLineIfLessThan

5

No Indent Keywords

Selection of language keywords that will not increase indentation.

DVT.textEditor.systemVerilog.formatting.indentation.noIndentKeywords

Open Scope Macros

List of macros that open a scope and increase the indentation of subsequent code.

DVT.textEditor.systemVerilog.formatting.indentation.openScopeMacros

[]

Optional Begin

Controls the placement of optional begin: Leave as is, On a new line, On the same line, On a new line and indent.

DVT.textEditor.systemVerilog.formatting.indentation.optionalBegin

“Leave as is”

Parameters

Controls the placement of module ports and parameters, function and task arguments, class parameters: Leave as is, One per line (open parenthesis on the same line), One per line (open parenthesis on the next line), More per line.

DVT.textEditor.systemVerilog.formatting.indentation.parameters

“Leave as is”

Preprocessing

Controls the indentation of preprocessing blocks: Leave as is, Indent, Indent and increase indentation level, Indent and increase indentation level except first, Move at first column.

DVT.textEditor.systemVerilog.formatting.indentation.preprocessing

“Leave as is”

Vertical Alignment

Compact Whitespace For Vertical Align Patterns

Controls whether consecutive whitespace characters are trimmed to a single space character for vertical align patterns.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.compactWhitespaceForVerticalAlignPatterns

false

Enable Vertical Align

Controls whether to enable vertical alignment.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.enableVerticalAlignment

false

Independent Preprocessing Scopes

Controls whether preprocessing scopes create independent alignment scopes.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.independentPreprocessingScopes

false

Only Consecutive Lines

Controls whether vertical alignment is applied only to consecutive lines.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.onlyConsecutiveLines

false

Vertical Align Patterns

Selection of additional code patterns for which vertical alignment is enabled: By Name Port Connections, Class Declarations, Class Declarations (split dimensions), Class Variable Declarations, Class Variable Declarations (split dimensions), `defines, Function Declarations, Function Declarations (split dimensions), Function Variable Declarations, Function Variable Declarations (split dimensions), Interface Port Declarations, Interface Port Declarations (split dimensions), Interface Signal Declarations, Interface Signal Declarations (split dimensions), Module Port Declarations, Module Port Declarations (split dimensions), Module Signal Declarations, Module Signal Declarations (split dimensions), `xvm_field macros.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignPatterns

 
{
   "By Name Port Connections": false,
   "Class Declarations": false,
   "Class Declarations (split dimensions)": false,
   "Class Variable Declarations": false,
   "Class Variable Declarations (split dimensions)": false,
   "`defines": false,
   "Function Declarations": false,
   "Function Declarations (split dimensions)": false,
   "Function Variable Declarations": false,
   "Function Variable Declarations (split dimensions)": false,
   "Interface Port Declarations": false,
   "Interface Port Declarations (split dimensions)": false,
   "Interface Signal Declarations": false,
   "Interface Signal Declarations (split dimensions)": false,
   "Module Port Declarations": false,
   "Module Port Declarations (split dimensions)": false,
   "Module Signal Declarations": false,
   "Module Signal Declarations (split dimensions)": false,
   "`xvm_field macros": false
}

Vertical Align Single Line Comments

Controls whether single line comments are vertically aligned.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignSingleLineComments

false

Vertical Align To Open Curly

Controls whether to vertically align relative to open curly.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignToOpenCurly

false

Vertical Align To Open Parenthesis

Controls whether to vertically align relative to open parenthesis.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignToOpenParenthesis

false

Vertical Alignment Tokens

List of tokens used for splitting lines in the same scope in vertically aligned columns.

DVT.textEditor.systemVerilog.formatting.verticalAlignment.verticalAlignTokens

[":=", "<="]

Line Wrapping

Enable Line Wrapping

Controls whether to enable line wrapping.

DVT.textEditor.systemVerilog.formatting.lineWrapping.enableLineWrapping

false

Line Width

Number of characters on a line after wrapping the line.

DVT.textEditor.systemVerilog.formatting.lineWrapping.lineWidth

80

Wrap Multi Line Comments

Controls whether multi-line comments are wrapped.

DVT.textEditor.systemVerilog.formatting.lineWrapping.wrapMultiLineComments

false

Wrap Single Line Comments

Controls whether single line comments are wrapped and moved above the code.

DVT.textEditor.systemVerilog.formatting.lineWrapping.wrapSingleLineComments

false