Indentation

• Optional Begin (DVT.textEditor.systemVerilog.formatting.indentation.optionalBegin) - Controls the placement of optional begin:

  • Leave as is (1)

  • On a new line (2) - begin is moved on a new line

  • On the same line (3) - begin is moved on the same line with it’s construct

  • On a new line and indent (4) - begin is moved on a new line and indented

Initial code	Leave as is (1)	On a new line (2)	On the same line (3)	On a new line and indent (4)

• Else (DVT.textEditor.systemVerilog.formatting.indentation.else) - Controls the placement of else:

  • Leave as is (1)

  • On a new line (2) - else is moved on a new line

  • On the same line (3) - if end precedes it, else is moved on the same line with end

Initial code	Leave as is (1)	On a new line (2)	On the same line (3)

• Parameters (DVT.textEditor.systemVerilog.formatting.indentation.parameters) - Controls the placement of module ports and parameters, function and task arguments, class parameters:

  • Leave as is (1)

  • One per line (open parenthesis on the same line) (2) - Each parameter/argument is placed on its own line and the open parentheses is placed on the same line with the parameter/argument receiver

  • One per line (open parenthesis on the next line) (3) - Each parameter/argument is placed on its own line and the open parentheses is placed on the next line after the parameter/argument receiver

  • Enable More Parameters Per Line If Less Than (DVT.textEditor.systemVerilog.formatting.indentation.enableMoreParametersPerLineIfLessThan) - It controls whether to place parameters on the same line when their number does not exceed a specified value. This option is available only when the Parameters preference is set to One per line (open parenthesis on the same line) or One per line (open parenthesis on the next line).

  • More Parameters Per Line If Less Than (DVT.textEditor.systemVerilog.formatting.indentation.moreParametersPerLineIfLessThan) - Parameters are placed on the same line if their number does not exceed this value.

  • More per line (4) - More parameters are placed on the same line

Note

When more parameters get to be placed on a single line and line wrapping is enabled, the parameters may be moved to separate lines as needed to fit within the specified line width.

Initial code	Leave as is (1)	More per line (4)

Initial code	One per line (open parenthesis on the next line) (3)	One per line (open parenthesis on the next line) (3) and More Per Line If Less Than set to “3”	One per line (open parenthesis on the next line) (3) and More Per Line If Less Than set to “1”

• Preprocessing (DVT.textEditor.systemVerilog.formatting.indentation.preprocessing) - This option affects preprocessing directives:

  • Leave as is (1)

  • Indent (2) - Indent the preprocessing directives according to the enclosing scope. `ifdef blocks don’t increase the enclosed statements indentation.

  • Indent and increase indentation level (3) - Indent the preprocessing directives according to the enclosing scope. `ifdef blocks increase indentation of its enclosed statements like any other scope language construct.

  • Indent and increase indentation level except first (5) - Indent the preprocessing directives according to the enclosing scope. `ifdef blocks increase the enclosed code indentation with the exception of the first nested preprocessing block.

  • Move at first column (4) - Move the preprocessing directives at line start. `ifdef blocks don’t increase the enclosed statements indentation.

Initial code	Leave as is (1)	Indent (2)	Indent and increase indentation level (3)	Indent and increase indentation level - except first (5)	Move at first column (4)

• Do Not Indent Single Line Comments At Beginning Of Line (DVT.textEditor.systemVerilog.formatting.indentation.doNotIndentSingleLineCommentsAtBeginningOfLine) - Controls whether to indent single line comments starting at the beginning of a line.

Before	After

• Indent Multi Line Comments (DVT.textEditor.systemVerilog.formatting.indentation.indentMultiLineComments) - Controls whether to indent multi-line comments.

Before	After

• Indent Multi-line Assigns (DVT.textEditor.systemVerilog.formatting.indentation.indentMulti-lineAssigns) - Controls whether to indent multi-line assigns.

Before	After

• Do Not Indent Multi-line Macro Definitions (DVT.textEditor.systemVerilog.formatting.indentation.doNotIndentMulti-lineMacroDefinitions) - Controls whether to indent multi-line macro definitions. This option is available only when the Preprocessing preference is set to Indent, Indent and increase indentation level, Indent and increase indentation level except first or Move at first column.

Before	After

• Add New Line After Begin And Before End (DVT.textEditor.systemVerilog.formatting.indentation.addNewLineAfterBeginAndBeforeEnd) - Controls whether to add a new line after begin and before end.

Before	After

• Add New Line After End (DVT.textEditor.systemVerilog.formatting.indentation.addNewLineAfterEnd) - Controls whether to add a new line after end.

Before	After

• Ignore Lines Starting With (DVT.textEditor.systemVerilog.formatting.indentation.ignoreLinesStartingWith) - List of line prefixes matching lines that will be ignored while indenting.

Before	After

• No Indent Keywords (DVT.textEditor.systemVerilog.formatting.indentation.noIndentKeywords) - Selection of language keywords that will not increase indentation.

Before	After (“assert” keyword)

• Implicit Semi Macros (DVT.textEditor.systemVerilog.formatting.indentation.implicitSemiMacros) - List of macros encapsulating semicolon or end delimiters.

Before	After

• Open Scope Macros (DVT.textEditor.systemVerilog.formatting.indentation.openScopeMacros) - List of macros that open a scope and increase the indentation of subsequent code.

Before	After

• Close Scope Macros (DVT.textEditor.systemVerilog.formatting.indentation.closeScopeMacros) - List of macros that close a scope and decrease the indentation of subsequent code.

Before	After